Intel® AVX and CPU Instructions

monitor/mwait disabled by IA32_MISC_ENABLES MSR?

Hi everyone, I'm having a strange issue, so I'll give a high-level description of it first, and then explain the details. I bought an Intel Xeon 5405 to put into my Mac Pro. It seems to work fine, but when I try to boot into Mac OS, I get a kernel panic claiming the CPU doesn't support the monitor/mwait instruction. I manage to remove the check from the boot process, and everything else seems to function normally. Out of curiosity though, I wrote myself a little utility to check the cpuid, and it gave me the following:

Instruction decoder

I'm working at the moment with decoding instructions for a given executable (windows or linux) or a part of memory. It can be described as a simple disassembler. Your manuals on Pentium processors are great help but I miss some of the most basic aspects of the processor architecture. (currently I've been using Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1, Basic Architecture and Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A, Instruction Set Reference)

Instruction decoder

I'm working at the moment with decoding instructions for a given executable (windows or linux) or a part of memory. It can be described as a simple disassembler. Your manuals on Pentium processors are great help but I miss some of the most basic aspects of the processor architecture. (currently I've been using Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1, Basic Architecture and Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A, Instruction Set Reference)

REAL(16) - long double

Are there any plans to implement the IEEE X_floating point (16 byte) with SSEn.m instructions?

Although this might not be suitable for mainstream (desktop) computing, it would be suitable for premium priced products. Intel does have premium priced product lines e.g. mmm Extreme. You could lable it at mmm Extreme+ and double the price.

Jim Dempsey

Documentation suggestion

This is a suggestion for the documentation relating to SSEn.m

1) Can you add a section that seperates the instructions by type of data. This section would essentially be an index and hyperlinks back to the alphabetical listing. I find it cumbersome to weed through the alphabetical listing.

SSEn.m Instructions by data type
Integer Byte
Integer Word
Integer Double Word
Integer Quad Word
Float
...
Double
...

assembly program in itanium based systems

Hi,

I'veHP-UX xxxxxxxx B.11.23 U ia64 in itanium processor. I want to write and analyse assembly program in itanium system. I can get the program by generating the assembly code using gcc -S option from C source code. I am not getting the meaning of the instruction as well as assembly program flow.If I get assembly code list, meaning of that perticular code as well as the role of that code in the program, it will be a very helpful to me. thank you

Why "subq" as allocate by ICC-v10.0 but not as prologue, but ICC-v11.0 uses "pushq" as prologue?

Hi All.

Below is a piece of CPP code and behaviour of asm due to ICC-v11.0 & ICC-v10.0 -

--
#include
#include

#define MAX 1024

int main()
{
int i, j;
int num[MAX], isort[MAX], cluster[MAX][MAX];

for (j = 0; j < MAX; j++) {
num[j] = 0;
isort[j] = j;
for (i = 0; i < MAX; i++) {
cluster[j][i] = 0;
}
}
printf("%d %d %d\n",num[64],isort[78],cluster[384][74]);
return 0;
}
--

Pages

Subscribe to Intel® AVX and CPU Instructions