Intel® Developer Zone:
Virtualization

Intel® Virtualization Developer Community

Developers, take advantage of Intel® VT. Engage with our bloggers and on the Forum, and tell us what is important to you. Let us know what is successful for you, and what opportunities we should action to make this site and the tools within, more helpful to your endeavors.

  • Getting Started
    • Intelligent Queueing Technologies for Virtualization Newly added & still relevant
    • Virtualization Primer New
    • Glossary of Virtualization Technologies
    • Virtualization Usage Models
    • Creating a Virtual Machine on VMware* Tutorial
    • Why Software Vendors Need to Care about Virtualization
    • Intel® Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices

    • Some helpful acronyms

      ATA Application Targeted Accelerators
      BMC Baseboard management Controller
      Boxboro Platform for Nehalem EX (Intel® Xeon® processor 7500 series and Tukwilla
      DCM Data Center Manager
      EP Efficient Performance
      EPT Extended Page Tables
      ESI Enterprise Southbridge Interface
      EX Expandable Server
      FBD Fully Buffered DIMM
      GT/s Giga transfers per second
      HA Home Agent in QPI based systems
      ICH IO controller hub
      IMC Integrated Memory Controller
      IOH IO hub
      L1, L2 Respectively the first and second level caches
      LA Land Grid Array(a type of chip packaginig0
      LLC Last Level Cache (on each chip) or Longest Latency Cache
      MC Mission Critical or Multi-core
      MC Memory controller
      ME Manageability engine
      NM Node Manger
      NUMA Non-uniform Memory Access
      OEM Original Equipment Manufacturer
      PCI Peripheral Component Interface (specification)
      QPI Quick Path Interconnect (Pt to Pt links)
      RAS Reliability, Availability, Serviceability
      RMCP Remote Monitoring and Control Protocol
      SCTP Stream Control Transmission Protocol
      SDDC Single Device Data Correction
      SKU Stock Keeping Unit (i.e., product variant)
      SMB Scalable Memory Buffer
      SMB SMBus System Management Bus
      SMI Scalable Memory Interface
      SMT Threads Simultaneous Multi-threading Threads or HW cpus on each core (2 if enabled, 1 if not)
      SSExy xy generation of vector instructions 9sTreaming SIMD extensions)
      TDP Thermal Design Power
      TPM Trusted Platform Module
      TPV Third Party Vendor
      Turbo Technology enabling higher frequency execution for one or more cores
      TXT Trusted Execution Technology
      Tylersburg Platform for Nehalem EP (Intel® Xeon® processor 5500 series) and Westmere EP(Intel® Xeon® processor 5600 series)
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Client Virtualization: Who, when, and why?
By David Ott (Intel)Posted December 15th 20090
I'd like to pose an open-ended question for interested readers to comment on. Much of the discussion I've heard surrounding virtualization technologies over the past few years pertains to servers. What about client virtualization?Q: Do you think client virtualization will catch on? Who, when, ...
Red Hat Virtualization Platform for Servers and Clouds
By Dawn M. FosterPosted November 9th 20090
Last week, Red Hat released Red Hat Enterprise Virtualization for Servers with comprehensive management tools that can be used for everything from servers in small businesses to ...
Cloud Computing at Red Hat and Novell
By Dawn M. FosterPosted October 26th 20091
I just ran across a blog post from Red Hat outlining some of the recent cloud computing developments at Red Hat, and it reminded me that Jeff Jaffe, Novell's CTO, had written a series of blog ...
Cloud Computing, Virtualization and Open Source on Intel
By Dawn M. FosterPosted October 19th 20090
In an earlier post, I mentioned that the Open Source at Intel website was going to have several focused topics about the intersection of Cloud ...

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Tracy CampFri, November 23rd 2012 - 19:05
How to identify processors with EPT accessed/dirty bits1
I'm aware that software can check the IA32_VMX_EPT_VPID_CAP MSR to determine if the EPT table supports access and dirty bits...  However I would like to know how to identify a processor before I've purchased it that has this support. This is a common frustration I have with Intel parts - minor ...
Ralf H.Mon, October 15th 2012 - 9:34
Unexpected EPT Violations1
Hi, we're currently working in a project that involves extending the KVM hypervisor. While running the VM, we sometimes get EPT violations that shouldn't be possible from our understanding of the Intel documents. The scenario is as follow (we use Intel VT with EPT enabled):All guest paging ...
kcav@snet.netWed, September 26th 2012 - 15:39
Technological migration and virtualization, are they complementary?2
Rather than force a user to abruptly break away from routines that have become easy to perform, I think it might be a good idea to run Windows 7 in a virtual environment on the new platform; provided it is possible to hotkey from the new work environment to the old, and back to the new in a New ...
Michael L.Thu, September 20th 2012 - 15:51
vmx-preemption timer inaccuracy (across vmx transitions)1
Hi, From what I understand, the VMX-preemption timer should only decrement when in VMX non-root operations. I have been trying to use it as a way to measure cycle time in a VM, with respect to the running time of that VM. Hence, I do not want to include in my measurement the time spent in the VMM ...

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Forum contributors

David Ott: a Senior Software Engineer with Intel's Software Solutions Group, David’s recent work focuses on various aspects of enterprise computing, including virtualization, energy efficiency, and security. David holds M.S. and Ph.D. degrees in Computer Science from the University of North Carolina at Chapel Hill.

Hussam Mousa is a Software Engineer with the System Optimization Technology Center (SOTC) at Intel. He works on virtualization performance analysis, focusing on I/O performance for enterprise class applications. He has several published papers on virtualization performance analysis in academic conferences. He received his PhD from the University of California Santa Barbara in 2010, and his Bachelors in Science from the American University in Cairo in 2002. He has been with Intel since 2007.

Karthik Narayanan is a software engineer at Intel working on enterprise and management applications, clustering, and high availability, on-demand computing, native and virtualized. His 4+ years at Intel were preceded with experience gained at software companies in NY and in India. Karthik earned his Bachelors in Engineering at Madras University, India; and his Master of Science in Computer Science at the University of Toledo.