AFAIK Intel has not provided any documentation about the peak ALU throughput of each EU. My understanding is that each EU has 2 FPUs, each capable of 8 flops/cycle (4 MACs per cycle per FPU pipe). Thus I am assuming 16 flops/cycle for 1 EU. Any clarification/confirmation would be great.
I hope it is not confidential information. For example, AMD and Nvidia both declare this information.
Public information is available on http://www.intel.com/p/en_US/support/highlights/graphics/cp3-hd4000 or http://intellinuxgraphics.org/.
You should also come to our webinar about Writing Efficient Code for OpenCL Applications on 3rd Generation Intel Core Processors. Where you will learn more.
Thanks,
Raghu
Thanks. I will look in the documentation. Yes, registered for the webinar :)