Nuevas instrucciones de AES
- Intel® AES New Instructions (Intel® AES-NI)
Descripción general de Intel® AES-NI, un conjunto nuevo de instrucciones de cifrado que mejora el algoritmo Advanced Encryption Standard (AES) y acelera el cifrado de datos.
- Protección de la empresa con Intel® AES-NI
Entérese por qué la criptografía está tan de moda en el mercado hoy en día, especialmente entre las empresas.
- Intel® Advanced Encryption Standard Instructions (AES-NI)
La descripción de las seis nuevas instrucciones que componen el conjunto de instrucciones de AES-NI y realizan varias partes del algoritmo AES de intensos cálculos computacionales.
Generador digital de números aleatorios
- Bull Mountain es el nombre de código asignado por Intel a su nueva instrucción de Arquitectura Intel® 64 RdRand y su implementación secundaria del hardware Digital Random Number Generator (DRNG). Bull Mountain proporciona una solución RNG basada en procesadores que es de alta calidad y desempeño, altamente disponible y segura.
Extensiones de conjuntos de instrucciones de la Arquitectura Intel®
- Intel® Memory Protection Extensions (Intel® MPX) es un nombre para las extensiones de la arquitectura Intel diseñadas para incrementar la robustez del software
- Intel® Software Guard Extensions (Intel® SGX) es un nombre para las extensiones de la arquitectura Intel designado para incrementar la seguridad del software mediante un mecanismo de “zona de pruebas inversa”
- Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) son una familia de siete instrucciones basadas en Intel® Streaming SIMD Extensions (Intel® SSE) que se utilizan juntas para acelerar el rendimiento del procesamiento de SHA-1 y SHA-256 en procesadores basados en la arquitectura Intel
Tecnología de virtualización Intel® (Intel® VT)
- Resumen técnico del hardware de virtualización
La Tecnología de virtualización Intel (Intel VT) proporciona hardware completo que le ayuda a mejorar el desempeño del software de virtualización, mejorar los tiempos de respuesta de la aplicación y proporciona mayor fiabilidad, seguridad y flexibilidad.
- Virtualización: Un amigo del desarrollador
Cuanto más usen los desarrolladores la virtualización, más usos encontrarán para esta tecnología. Descubra lo que le faltaba y cómo la virtualización puede ayudarle a hacer mucho más.
- Tecnología de virtualización Intel® Animación Flash*
Esta animación proporciona una descripción general de la Tecnología de virtualización Intel®, la cual es una técnica mediante la cual los recursos de hardware se pueden resumir, dividir y compartir entre varios entornos de sistemas operativos que se ejecutan simultáneamente.
- Tecnología de virtualización Intel® Prácticas recomendadas para proveedores de software
Esta serie de artículos funciona como una ayuda para ayudar a los proveedores de software a ajustar sus aplicaciones para utilizarlas con Intel VT.
Overview As companies continue to strive to meet expanding goals with smaller budgets, they increasingly turn to virtualization as a means to consolidate servers. Successful reduction in server count by these means enables organizations to decrease capital expenditures in the form of equipment an...
To VT-D or Not to VT-D? A guide on whether to Utilize Direct Device Attach in your Virtualized System?
By Hussam Mousa (Intel)Posted 02/02/20121
Intel VT-D Direct Device Attach allows a Virtual Machine to control an entire PCI-E device (e.g. NIC) while bypassing any VMM interference. The performance benefit will be a dramatic reduction in CPU utilization, but the precise gain will vary.
Intel® Active Management Technology on Virtualized PCs: Expected behavior and Best Known Methods for using Intel® AMT with client virtualization
Abstract There are several key differences one must consider when using Intel Active Management Technology (Intel® AMT) features on a virtualized client. Those differences, along with Intel’s recommendations, are discussed in this article. It is important to understand those differences in order ...
By robert-adams (Intel)Posted 02/01/20124
Use of virtual worlds for training, entertainment, and collaboration is growing. Intel Labs has been researching the scalability of virtual worlds. This series explores some of the design, performance, and execution features of virtual world servers.
By David Ott (Intel)Posted 11/23/20100
Part 7: Enterprise Security Applications While trusted computing represents a significant step forward in insuring an uncompromised software environment, it should not be understood as a replacement for the many other security applications protecting a user's platform. The distinction to be noted...
By David Ott (Intel)Posted 11/22/20100
Part 6: Implications for Software Developers: Cloud Management Software While the scope of trusted computing may seem limited to an individual computer, one might also consider the broader context of public or private data centers and cloud computing. Among a data center's hosting options might b...
By David Ott (Intel)Posted 11/08/20100
Part 4: Intel® TXT So where does Intel fit into the picture? Intel® Trusted Execution Technology (Intel® TXT) is Intel's flagship technology for making possible the implementation of the trusted computing vision described above. TXT, as a collection of technologies, is quite complex, but a sum...
By David Ott (Intel)Posted 11/03/20101
Part 3: The Trusted Platform Module (TPM) The TPM, as defined by TCG, is a multi-function hardware unit solving a number of problems related to the context of trusted computing. In simplistic terms, the TPM can be thought of as a cryptographic co-processor with a secure integrity measurement s...
During vmlaunch/vmresume, several checks are performed on the guest state area. I was wondering if anyone else had noticed that Guest RSP field is never checked for a non-canonical address. The virtualization spec talks about such checks for Guest RIP or GDTR or IDTR. I was wondering why this check was not done for the Guest RSP?
By Yogi D.1
Hi. I am writing a small OS-agnostic hypervisor as a teaching tool for my students. The hypervisor code is loaded by the code I embed in a custom MBR on the boot device when the system boots. The hypervisor code switches to 32-bit proected mode and then IA32e (64-bit mode). It then sets up the hypevisor, EPT to protect the hypervisor from the guests, and launches a 16-bit "unrestricted" big real-mode (or unreal mode) guest. All this is working perfectly. The guest can make BIOS calls. The hypervisor writes directly to the video buffer in order to provide debugging/status info. The hypervisor is setup to VMexit minimally (e.g., I/O, APIC, MSRs, etc. are not monitored -- yet). When the real-mode guest causes EPT violations, issues CPUID, etc. these cause VMExits as expected and the hypervisor handles them and resumes the guests. When the 16-bit guest issues an INIT IPI to itself using the APIC, I run into an infinite VMExit situation that my hypervisor cannot seem to recover ...
By Tyler T.0
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By Tracy Camp1
I'm aware that software can check the IA32_VMX_EPT_VPID_CAP MSR to determine if the EPT table supports access and dirty bits... However I would like to know how to identify a processor before I've purchased it that has this support. This is a common frustration I have with Intel parts - minor features vary quite a bit and don't seem to necissarily 'stick' in a linear progression of CPUID values due to various market differentiations. Most of the time it doesn't matter too much, since most features are just an optimization for something that doesn't need to be implemented in software, however in this particular case, I'm not sure how to 'emulate' the lack of an accessed and dirty bit in the EPT tables of earlier EPT implementations in software.
By Ralf H.1
Hi, we're currently working in a project that involves extending the KVM hypervisor. While running the VM, we sometimes get EPT violations that shouldn't be possible from our understanding of the Intel documents. The scenario is as follow (we use Intel VT with EPT enabled):All guest paging structures (i.e., the paging structures _inside_ the VM) are set to non-writable on the last EPT level. In other words, whenever the guest OS writes to a guest paging structure (e.g. to map/free a page), this triggers an EPT violation. Now, "occasionally" the following happens:The VM performs a normal read operation somewhere in memory (doesn't seem to matter where). This then yields an EPT violation and bit 0, bit 1, and bit 7 are set in the exit qualification field, bit 8 is cleared. According to the Intel specification (Table 27-7), this means that the EPT violation was caused by the MMU setting the dirty or accessed bit in the guest paging structures. At first, this makes sense since these ar...
Rather than force a user to abruptly break away from routines that have become easy to perform, I think it might be a good idea to run Windows 7 in a virtual environment on the new platform; provided it is possible to hotkey from the new work environment to the old, and back to the new in a New York minute. My interest in this came about when after changing from an old fashion notebook to an Ultraboook with a Touch screen I discovered the Start menu has changed, of course. Also, I realized that using a slow browser on a fast platform doesn’t make sense, so I left behind my beloved IE8 with iGoogle homepage and changed to speedy Google Chrome. Then I found myself wondering how to save Favorites, block pop-ups, establish and maintain trust relations, all things I had become somewhat familiar with doing, and now have to consciously think about again. I am looking forward to making greater use of audio and video processing capabilities in the new 64-bit environment. Since A/V file...
By Michael L.1
Hi, From what I understand, the VMX-preemption timer should only decrement when in VMX non-root operations. I have been trying to use it as a way to measure cycle time in a VM, with respect to the running time of that VM. Hence, I do not want to include in my measurement the time spent in the VMM or the time to perform VM entries/exits. VMX-preemption timer seems like it could serve that purpose (with the granularity of the TSC to VMX-preemption timer ratio). However, in my test, the VMX-preemption timer seems to also decrement while performing VM entry/exits. My test: a) from the VMM: read the VMX-preemption timer in the VMCS b) VM enter c) VM exit *immediately after VM enter* (eip set to the hlt instruction) d) from the VMM: read the VMX-preemption timer in the VMCS (processor setup to save the VMX-preemption timer to VMCS on VM exit) the difference between (d) and (a) should be zero or a very small value since the VMX-preemption timer should only be decrementing when executing i...
no wonder it possible for professionals to adanay kalanagn desktop and server virtualization, but it is very confusing for the layman, because it is almost like it is just different in the context of network and local only. desktop virtualization is more focused on the dektop without touching the network between computers, such as, VMWare Player, Virtualbox, Qemu, etc.. very useful for testing the OS on the client. server virtualization is more directed to the network as it relates to the Internet or a network cable or wireless jaringn keuntunganya further test of seranagn hackers because networks are vulnerable from attacks hercker! no wonder it possible for professionals to adanay kalanagn desktop and server virtualization, but it is very confusing for the layman, because it is almost like it is just different in the context of network and local only.desktop virtualization is more focused on the dektop without touching the network between computers, such as, VMWare Player, Virtual...