Sometimes when we vectorize a loop, we get a high Clocks Per Instruction Retired (CPI) value. This happens when there is high bus utilization and the bus gets saturated.
SSE3
How to Become Familiar with Streaming SIMD Extensions 3 Instructions
Challenge
Become familiar with SSE3 Instructions. SSE3 for the 32-bit Intel® architecture is a set of 13 new instructions that accelerate performance of Streaming SIMD Extensions (SSE) technology, Streaming SIMD Extensions 2 (SSE2) technology, and 87-FP math capabilities. The new technology is compatible with existing software written for Intel architecture microprocessors, and existing software should continue to run correctly, without modification, on microprocessors that incorporate SSE3 instructions.
How to Satisfy the System Programming Model for Streaming SIMD Extensions 3 Instructions
Challenge
Satisfy system-programming model and requirements for SSE3 instructions. The SSE3 Instructions state requires no new OS support for saving and restoring the new state during a context switch, beyond that provided for Streaming SIMD Extensions (SSE).
How to Use the MONITOR and MWAIT Streaming SIMD Extensions 3 Instructions
Challenge
Implement SSE3 instructions to improve synchronization between multiple agents. This technique is targeted for use by system software to provide more efficient thread-synchronization primitives.
How to Implement ADDSUBxx Streaming SIMD Extensions 3 Instructions
Challenge
Implement SSE3 single-precision and double-precision packed ADDSUBxx instructions. ADDSUBPS has two 128-bit operands. The instruction performs single-precision addition on the second and fourth pairs of 32-bit data elements within the operands and single-precision subtraction on the first and third pairs. This instruction is effective at evaluating complex products on packed single-precision data.
Streaming SIMD Extensions 3 Enabling for the Microsoft .NET* Compiler 2003
Introduction
By James Rose
Sr. Application Engineer
CSD/AET Client Enabling Technology
