I'm excited by our announcement today of Intel® Parallel Computing Centers. The first five centers will be located at CINECA, Purdue University, Texas Advanced Computing Center at the University of Texas (TACC), The University
The following is a compendium of research publications from Intel Labs focused on optimization of High Performance Computing (HPC) algorithms for improved performance on Intel(R) Xeon(R) processors and Intel(R) Xeon Phi(tm) Coprocessors. We will continue to update this list as new publications are posted.
Scheduling for 1-4 Threads Per Core Using Compiler Option
This option is a hint or suggestion to the compiler about the number of hardware threads per core that MAY be used for an application. This hint enables the compiler to perform better code optimizations (such as instruction scheduling).
By Mikhail Smelyanskiy, Jason Sewall, Dhiraj D. Kalamkar, Nadathur Satish, Pradeep Dubey, Nikita Astafiev, Ilya Burylov, Andrey Nikolaev, Sergey Maidanov, Shuo Li, Sunil Kulkarni, Charles H. Finan, Ekaterina Gonina