FAQ

FAQ

Ritratto di James Reinders (Intel)
James Reinders (Intel)
Mer, 23/05/2012 - 10:32

Welcome to this forum.

This forum is for discussion of the Intel Many Integrated Core (MIC) Architecture and the Intel Xeon Phi coprocessor.

Q. Where can I read more about MIC?

Here are a few places:

Q. What if I have more questions?
A. Read this FAQ and search this forum. If neither answer your question, please post a question on the forum.

Q. What ISVs have announced application support for the Intel Xeon Phi coprocessor?
A. Refer to MIC architecture support by software tools for a list of vendors who have announced support so far.

Q. Why not use a standard Linux distribution to run on the card?
A. Every standard Linux distribution supports processors for which work was done previously to add support. We have added support for the Intel Xeon Phi coprocessor. This meant supporting a number of micro-architectural features, the Intel Xeon Phi ISA, Intel Xeon Phi ABI and adding support for coprocessor mode (drivers).

Q. Are optimizations for Intel Xeon Phi coprocesors beneficial for processors (e.g., Intel Xeon processors)?
A. The keys to a good application for Knights Corner are the same as for an Intel Xeon processor: scale and vectorize. Pick a method to scale (OpenMP, MPI, TBB, etc.). Pick a method for vectorization (compiler options, pragmas, Cilk Plus, etc.). Tune. Many results from tuning on a MIC architecture machine have proven to increase performance on the original target as well.

Q. Are Intel Xeon Phi coprocessors binary compatible with other processors?
A. The unique combination of new features in Knights Corner, and the software stack for Knights Corner, mean that no binaries prior to Knights Corner are completely compatible with Knights Corner nor would they take advantage of the new Knights Corner vector instructions and the four-way multithreading of the hardware.

Q. How do I contribute to open source support for Intel Xeon Phi coprocessors or MIC?
A. With regards to the capabilities we have released on this forum (see RESOURCES thread, our efforts will eventually be incorporated in the open source projects themselves. Today, feel free to start a discussion on this forum with ideas, questions or patches. With regards to other project, feel free to work with any project out there to propose patches. Starting a thread in this forum to find like-minded developers is encouraged.

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Ritratto di jimdempseyatthecove
jimdempseyatthecove
Mar, 05/06/2012 - 04:38

Hi James,

Your first two links to reference articles result in Page Not Found :(

Jim Dempsey

Blog: The Parallel Void

www.quickthreadprogramming.com
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Ritratto di James Reinders (Intel)
James Reinders (Intel)
Mar, 05/06/2012 - 11:34

I fixed this morning, thank you for bringing it to my attention. - james

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Ritratto di R Lloyd Rankin
R Lloyd Rankin
Dom, 09/09/2012 - 15:27

If, as you say, the Knight's Corner, Xeon Phi, etc. is not binary compatible with prior Intel processors the "same instruction set" argument goes out the window. Using the Xeon Phi is still heterogeneous parallel processing. Not entirely evil unless you're one of those don't believe that "the free lunch is over". This isn't easy and it's not going to get easier fast. You may hear otherwise but that is usually from someone trying to sell you some snake oil that will make it easy. It takes intelligence, knowledge and effort which is job security for the talented programmer.

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Ritratto di James Reinders (Intel)
James Reinders (Intel)
Lun, 10/09/2012 - 02:06

A *key* feature of Intel Xeon Phi coprocessors is the 512 bit SIMD capbility. This is the first Intel product with such support, and as such a binary using 512 bit vectors cannot run on other processors. When we introduced MMX, SSE and AVX (64 bits, 128 bits, 256 bits) - we created the same challenge: a processor with a abilities to run code that ran nowhere else (for a while). "same instruction set" is about a base and adding feature to the base. Intel processors have added features for a long time, but benefitted from having the same "base." A static instruction set would fail to stay relevant. Rather than beat around the bush, I've been clear that 512 bit is important, and as such the binaries you run won't run elsewhere (at this time). Of course, being on a card and running Linux gives you a coprocessor model which is new enough to not match existing binaries in any case. So I pushed on the "not binary compatible." However, we certainly have source code compatibily options - and the base instruction set is the same, which turns out to be very helpful. For one thing, porting is in general trivial - leaving primarily only the challenges of parallel programming after porting. Ah, those. No magic there... but rewarding payoffs on a high parallel device when you give it highly parallel work.

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Ritratto di dchabaud_optis_world_com
dchabaud_optis_world_com
Lun, 15/10/2012 - 02:17

Hi James,
We met Suresh Rangarajulu from INTEL at the Siggraph who was interested by our applications, I am trying to contact him without any success.
We develop Physics Based Lighting Simulation software, we are integrated in Catia V5, SolidWorks, CREO. Our simulations are perfectly scalable and run on multi-processors/multi-cores CPU or GPU. On CPU, we already test our application on 32 threads and it runs perfectly. We thing we could be an active partner for MIC and Knights Corner. Can you suggest a contact at INTEL?
D. CHABAUD
VP R&D
dchabaud@optis-world.com
http://www.optis-world.com/

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Ritratto di James Reinders (Intel)
James Reinders (Intel)
Lun, 15/10/2012 - 15:10

I will let Suresh know you want him to contact you.

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Ritratto di AlexHK
AlexHK
Lun, 11/03/2013 - 01:20

Hi James,

this info is outdated, insn't it (ie. no. of cores, pricing, shipping date etc)?

Don't shoot the messenger in case I am wrong, I am just familiarizing myself withe the forums before posting.

Alex

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Ritratto di James Reinders (Intel)
James Reinders (Intel)
Lun, 11/03/2013 - 09:41

Sorry, yes, updated!

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Ritratto di chenwg2000
chenwg2000
Mar, 19/03/2013 - 10:07

Hello, can you share hpl source code for mic? In composerxe, I have found that on mic or host cpu, But now I want to make use of both at the same time. Either offload or MPI is OK.

Thanks

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