Ivy Bridge has a cache line with length 64 bytes. Suppose I have 4 array on 4 different memory addresses, when I load the first 128bit in each array to 4 SSE registers respectively, then I have loaded 4 cache lines? How many cache lines available?
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>>How many cache lines available?
For example, for Intel(R) Core(TM) i7-3840QM:
L1: 256KB -> ( 32KB per core for data & 32KB per core for instructions ) x 4 cores
L2: 1024KB -> ( shared for data & instructions 256KB per core ) x 4 cores
L3: 8192KB ( 8MB ) -> ( shared for data & instructions & between all cores / 8 logical )
Sizes of these cache lines are different and it depends on a CPU. Please take a look at datasheets at: http://ark.intel.com.