Selective Use of gatherhint/scatterhint Instructions
This note documents a known hardware issue with early alpha hardware of the Intel® Xeon® Phi™ coprocessor (A0 stepping from 2011) and an undocumented option to work around it.
Scheduling for 1-4 Threads Per Core Using Compiler Option
This documents a compiler option that affects the number of hardware threads per core that will be used by an application.
-mCG_lrb_num_threads=1|2|3|4 (default is 2) ( Composer XE 2013 initial release, version 13.0.0.079. undocumented/unsupported option )
In this chapter, we examine the Intel® Composer XE 2013 Heterogeneous Offload programming model for the Intel® MIC Architecture.