Commission Shortcut Review released by the maydayreport representing Mike Daniels's newly released Commission Shortcut encode.
Virtualization Software Development
Looking for SINIT AC Module for E5-2670
can't find it from the official list: http://software.intel.com/en-us/articles/intel-trusted-execution-technology/
i7 3930K C2 stepping confusion over EPT
Hi, There is some confusion over if the i7 3930K C2 stepping can support EPT as part of its VT-x abilities. Some of the martieral on the Intel site say no while others have said that it does depending on the motherboard used. Could someone please clarify? Thanks, David.
Finding out if "Unrestricted Guest" supported at runtime
Hi there,
is there an option to find out at runtime (e.g. with means of CPUID or something else) if the "Unrestricted Guest" feature is supported on the CPU? In the developer manual I can only find which flags control the UG feature (i.e. "25.8. Unrestricted Guests" ff), but I don't see anywhere how to determine if the feature is actually supported. Historically, at which processor family was "Unrestricted Guest" introduced? Is there a easy way to tell which processors contian the feature from the timeline?
Best regards,
Joe
Is it possible to use Intel NPT to do cross ISA memory translation?
O.K., I know Intel virtualization techniques are used to help better performance for same ISA, i.e., x86, virtualization. But I am curious if we can use NPT to help us to do cross ISA memory translation. For example, I can run a ARM guest on x86 host by using QEMU, but the memory translation inside QEMU is pure software. Is it possible to leverage underlying hardware to speedup the translation?
Any comments are welcome. Thanks!
How to manually do VM exit in the guest?
I need to define a new exit reason of my own and want to set the exit reason in VMCS before switching to the host KVM module,then do something in KVM hypervisor for this reason.But I notice the vmcs_writel() is static,how can I do it?
Performance Counter Uncore issues
Trying to implement performance counting on my bare-metal hypervisor. Particularly I am interested in the L3 cache misses for an intel i7 06_1Eh processor. There are two methods that should give me the same result, the non-architectural MEM_LOAD_RETIRED.L3_MISS performance event and the uncore UNC_l3_MISS.ANY performance event. I assign either of these events to the IA32_PERFEVTSEL0, set the USR, OS, and EN bits, or the MSR_UNCORE_PERFEVTSEL0 setting the EN bits. And then I set their respective enable bits in their respective global performance control MSRs.
Cloud Computing Via Virtualization
Dear Friends,
Now a Days Cloud Computing takes a lead in IT industry. We all Knows How Cloud Works.
First We need to setup one server that creats main node or cluster (Master) and Others are Supporting Node.
I have some idea about Infrastructure as a service via Ubuntu server.
In
IaaS we have some Actual Processors and Chunks of Hardware but Through
Virtualization We can Create a Node. And Friend If You have any Idea
About Clusters,Nodes and Virtual Server than You can Post Here.
Now a days i m developing Cluster Monitoring System.
Cloud Computing Via Virtualization
Dear Friends,
Now a Days Cloud Computing takes a lead in IT industry. We all Knows How Cloud Works.
First We need to setup one server that creats main node or cluster (Master) and Others are Supporting Node.
I have some idea about Infrastructure as a service via Ubuntu server.
In IaaS we have some Actual Processors and Chunks of Hardware but Through Virtualization We can Create a Node. And Friend If You have any Idea About Clusters,Nodes and Virtual Server than You can Post Here.
Now a days i m developing Cluster Monitoring System.
performance counter question
Can rdpmc be used to read the uncore performance counters for an i7 processor? Or is the only way to read them through the MSR?
Pagine
