The purpose of this blog (from: Phil Thierry and Leo Borges - part of the Intel SSG Energy Engineering Team and covering Oil and Gas technical activities ) is to start a discussion about implementation for 3D seismic wave propagation and. more specifically, for the Reverse Time Migration (RTM) algorithm as a whole on one, two or several Intel® Xeon Phi™ coprocessors in a full hybrid mode, i.e. including full utilization of the CPU cores.
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Download Intel® Xeon Phi™ Coprocessor Developer's Quick Start Guide [PDF 763KB]
The first Intel® Many Integrated Core (Intel® MIC) architecture product
George Chrysos, Intel Corporation
This whitepaper is a transcription of George Chrysos’ presentation at the Hot Chips conference held in September 2012, covering details about the Intel® Xeon Phi™ coprocessor, more specifically the first generation product (codenamed Knights Corner). Note that the results quoted in this paper were measured in development labs at Intel Corporation on prototype hardware and systems.
Identifying software coding issues on a high-performance computing targeted platform often requires accessing the system remotely or through firewalls. In these cases it may be desirable to minimize the bandwidth overhead created by the feature-rich Elicpse* IDE integrated user interface or it’s Eclipse* Rich Client Platform based standalone user interface.
The solution provided for these use cases consists of two command-line debuggers.
The Intel® Composer XE 2013 for Linux* includes the Intel® Debugger, which provides several approaches to analyzing and tracking down coding issues for heterogeneous applications that run on a host system and create offload processes on the Intel® Xeon Phi™ Coprocessor. In addition, the Intel® Debuggers permit debugging of coprocessor code only.
The three debug solutions supporting Intel® Xeon Phi™ Coprocessor available are
At the International Supercomputing Conference (ISC'12) in Hamburg, Germany, Intel announced that Intel® Xeon Phi™ is the new brand name for all future Intel® Many Integrated Core Architecture (Intel® MIC Architecture) based products. Targeted at supercomputers, Intel® Xeon Phi™ Coprocessor will have up to 61 cores and deliver power consumption breakthroughs while scaling performance when conducting complex scientific calculations.
As with most computing systems, the Intel® Many Integrated Core Architecture programming model can be divided into two categories: application programming and system programming.
In this guide, application programming refers to developing user applications or codes using either the Intel® Composer XE 2013 or 3rd party software development tools. These tools typically contain a development environment that includes compilers, libraries, and assorted other tools.
Monte Carlo uses statistical computing method to solve complex scientific computing problems. It innovatively uses random numbers to simulate the uncertainty of inputs to a problem and makes use of computer to process the repeated sampling of the parameter to solve the problem that otherwise impossible to obtain a deterministic result. This method was originally pioneered by nuclear physicists involved in Manhattan projects in late 40s. It is named after the biggest casino in the principality of Monaco.
A number of tool vendors have announced they will be providing versions of their software tailored to supporting Intel(R) Many Integrated Core Architecture, starting with the Intel(R) Xeon Phi(tm) coprocessor. Please contact the vendors directly for details about versions supported on Intel(R) Xeon Phi(tm) coprocessor.
This is a "living" document that will be updated as more software becomes available