Courseware - Computer Architecture and Organization

Overview of the history of the digital computer
Introduction to instruction set architecture, microarchitecture and system architecture
Processor architecture – instruction types, register sets, addressing modes
Processor structures – memory-to-register and load/store architectures
Instruction sequencing, flow-of-control, subroutine call and return mechanisms
Structure of machine-level programs
Limitations of low-level architectures
Low-level architectural support for high-level languages

Introduction to multicore architecture (VTU)

Material Type:	Lecture / Presentation
Technical Format:	PDF document
Location:	Go to materials
Date Added:	02/24/2011
Date Modified:	02/24/2011
Author	H.S. Jamadagni, Visvesvaraya Technological University (VTU)
Description: Introduction to multicore architecture: Evolution of Computer Architecture Trends; Fundamentals of Parallel Computers; Need for multicore architectures
Recommended Audience:	Beginning programmers, Undergraduate students
Language:	English
Keywords:	multicore, Power, Quick Path Interconnect

MULTICORE ARCHITECTURES (VTU)

Material Type:	Article / White paper
Technical Format:	PDF document
Location:	Go to materials
Date Added:	02/24/2011
Date Modified:	02/24/2011
Author	H.S. Jamadagni, paul.f.steinberg@intel.com
Description: This chapter from Visvesvaraya Technological University (VTU) intends to provide an overview on multicore architectures. The chapter discusses the evolution of the architecture leading to multicore architecture. The generic block diagram of a multicore architecture is discussed followed by Intel Multicore Architecture.
Recommended Audience:	Beginning programmers, Undergraduate students
Language:	English
Keywords:	multicore, Moore's Law, Parallelism

Integrated Architecture and Tools - Cilk Plus Revision

Material Type:	Lecture / Presentation, Coding example, Workshop and Training Materials
Technical Format:	Powerpoint presentation, zip archive, Word document
Location:	Go to materials
Date Added:	12/14/2010
Date Modified:	12/14/2010
Author	Robert Chesebrough, Intel
Description: The module interleaves compiler and performance analyzer topics with essential architecture topics. General architecture topics include: Exploiting the architecture - taking advantage of: SSE how to get instructional parallelism in a single core. Multi-core architecture: how to use OpenMP and or Intel® CilkPlus™ to get parallelism from multiple cores Program organization via cache utilization, efficient data structures and loop performance.
Recommended Audience:	Advanced programmers, Beginning programmers, Undergraduate students
Language:	English
Keywords:	ISA, MIPS, ALU, design, microarchitecture, pipelining, cache, VM, Verilog, memory hierarchy

Intel® Processor Micro-architecture– Core®

Material Type:	Lecture / Presentation
Technical Format:	Powerpoint presentation
Location:	Go to materials
Date Added:	09/30/2010
Date Modified:	09/30/2010
Author	Michael Pearce, ISE
Description: This is a powerpoint presentation that was referenced in the IAC forum: http://software.intel.com/en-us/forums/showthread.php?t=66127&o=d&s=lr
Recommended Audience:	Beginning programmers, Graduate students
Language:	English
Keywords:	Core, architecture

EE 352 Computer Organization and Architecture

Material Type:	Metasite / Reference material
Technical Format:	RTF document
URL:	Go to URL
Location:	Go to materials
Date Added:	05/17/2010
Date Modified:	05/17/2010
Author	Mark Reddekop, USC
Description: EE 352 Computer Organization and Architecture has been modified and covers: exploiting parallelism strategies, cache mapping schemes, and the computer organization and architecture, and how those components are interrelated. The new course emphasizes the performance impact that multi-core hardware imposes on both sequential and parallel programs. The class used Ubuntu Linux; VTUNE will be included in the courseware in the Fall 2010. 55 students enrolled in this course. University of Southern California – EE352 Computer Organization and Architecture.
Recommended Audience:	Undergraduate students
Language:	English
Keywords:	Syllabus, Computer Architecture and Organization

Program Optimization for Multi-core Architectures (Indian Institute of Science, Bangalore)

Material Type:	Lecture / Presentation
Technical Format:	Word document, zip archive
Location:	Go to materials
Date Added:	04/14/2010
Date Modified:	04/14/2010
Author	Indian Institute of Science Bangalore, 2009,
Description: The course will cover the following: Processor architectures with focus on memory hierarchy, instruction level parallelism and multi-core architectures Program analysis techniques for redundancy removal and optimization for high performance architectures Concurrency and operating systems issues in using these architectures Programming techniques for exploiting parallelism (use of message passing libraries) Tools for code analysis and optimization (Intel compilers, profilers and application tuning tools What do we expect to achieve by the end of the course? Faculty who can teach this course and conduct research in this area Students who can design, develop, understand, modify/enhance, and maintain complex applications which run on high performance architectures (in addition to doing research!) A set of slides, notes, projects and laboratory exercises which can be used for teaching this course in future both at IITK and at other universities
Recommended Audience:	Undergraduate students
Language:	English
Keywords:	Optimization, Multicore, Architectures

Computer Architecture (U of Mich)

Material Type:	Lecture / Presentation
Technical Format:	PDF document, Word document, zip archive
Location:	Go to materials
Date Added:	04/01/2010
Date Modified:	04/01/2010
Author	Dr. David Blauuw, University of Michigan Dr. Rich Brown, University of Michigan Dr. Michael Flynn, University of Michigan; Intel Higher Education Dr. Dennis Sylvester, University of Michigan
Description: This is an introductory graduate-level course in computer architecture. This course is intended to do two things: provide a solid, detailed understanding of how computers are designed and implemented, including the central processor and memory and I/O interfaces; and to present the numerous tradeoffs in design and implementation, system interaction, realization in both historical and state-of-the-art systems, and trends that will affect future systems. It covers instruction set architectures, pipelining (including basic pipelining, multiple-instruction-per-cycle machines, out-of-order instruction execution, and vector processing), memory systems (including caches and virtual memory), I/O interfaces, operating system issues, basic multiprocessor systems, and power reduction techniques. This course is part of The VLSI Curriculum includes content for 16 undergraduate and graduate courses that were provided by the Electrical Engineering and Computer Science Department at the University of Michigan.
Recommended Audience:	Graduate students
Language:	English
Keywords:	Computer, Architecture

Intel® Developer Zone

Intel® Developer Zone:
Courseware - Computer Architecture and Organization