MEM_UOP_RETIRED. LOADS & MEM_UOP_RETIRED. STORES

MEM_UOP_RETIRED. LOADS & MEM_UOP_RETIRED. STORES

Аватар пользователя GHui
GHui
ср, 28/03/2012 - 02:12

I want to collect MEM_UOP_RETIRED. LOADS and MEM_UOP_RETIRED. STORES events. I used "perf stat -e r01D0 -e r02D0 ./stream" to test. But I get event's value is zero. I dont't known how this happened.

OS: rhel6.1
HardPlatform: vendor_id: GenuineIntelcpu family: 6model: 45model name: Intel Xeon CPU E5-2680 0 @ 2.70GHzstepping: 6cpuid level: 13

------------------------------------------------------------------------------------
EventNum. | UmaskValue | EventMaskMnemonic | Description | Comment
------------------------------------------------------------------------------------
D0H | 01H |MEM_UOP_RETIRED.LOADS | Qualify retired memory uops that are loads. Combine with umask 10H,20H, 40H, 80H. | Supports PEBS
------------------------------------------------------------------------------------
D0H | 02H |MEM_UOP_RETIRED.STORES | Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. |
------------------------------------------------------------------------------------

I get the doucument from http://download.intel.com/products/processor/manual/325462.pdf, at page 3121/4128.

--GHui
RSS Вверх
6 сообщений / 0 новое
Последнее сообщение
Пожалуйста, обратитесь к странице Уведомление об оптимизации для более подробной информации относительно производительности и оптимизации в программных продуктах компании Intel.
Аватар пользователя GHui
GHui
чт, 29/03/2012 - 09:05

And may I consider the two events (MEM_UOP_RETIRED. LOADS & MEM_UOP_RETIRED. STORES) as memory bandwidth?

--GHui
Вверх
Аватар пользователя Patrick Fay (Intel)
Patrick Fay (Intel)
чт, 29/03/2012 - 09:58

Hello GHui,
You need to use the umask '0x81' for loads and 0x82 for stores.
From the SDM vol 3:

evt=D0H, umask=80H, MEM_UOP_RETIRED.ALL ; Qualify any retired memory uops.; Must combine with umask 01H, 02H, to produce counts.

So for loads use '-r81d0' and for stores use -r82d0.

The events just countloads and stores uops, not necessarily loads and stores that go all the way to DRAM.
And, probably unless your code is hand coded assembly (where you KNOW that all the loads go to DRAM, no register spills, reloading of registers etc) then probably most loads and stores don't go memory(DRAM).
Pat

Вверх
Аватар пользователя GHui
GHui
пт, 30/03/2012 - 00:07

Yes, it worked. Thank you.

(240257946213*64*10e-9 + 120170251833*64*10e-9)/165.653999299 = 139.250514763052

I calc the MemoryBandwidt is 139GB/sec, is that correct according to the stream log?

The output log follow:
----------------------------
Function Rate (MB/s) Avg time Min time Max time
Copy: 14224.0068 0.0068 0.0067 0.0071
Scale: 13815.0410 0.0070 0.0069 0.0073
Add: 15270.5243 0.0095 0.0094 0.0099
Triad: 14748.1204 0.0098 0.0098 0.0101
-------------------------------------------------------------
Solution Validates
-------------------------------------------------------------

Performance counter stats for './stream':

240257946213 raw 0x81d0
120170251833 raw 0x82d0

165.653999299 seconds time elapsed

--GHui
Вверх
Аватар пользователя GHui
GHui
пт, 30/03/2012 - 02:28

I also tested Linpak.

(3007370989069*64*10e-9 + 96836841041*64*10e-9)/143.245665508 = 1386.913177599393

The result is so big that I think there is something wrong with my formula.

The linpak log following:

----------

[ user ]$ perf  stat -e r81d0 -e r82d0 ./linpack
   ... ...

   ... ...
    3007370989069  raw 0x81d0

    96836841041  raw 0x82d0
  143.245665508  seconds time elapsed

--GHui
Вверх
Аватар пользователя Patrick Fay (Intel)
Patrick Fay (Intel)
пт, 30/03/2012 - 08:10

The only way you can use these events to count memory bandwidth is if you are SURE that every load and store uop actually misses the L3.
Your results indicate that most of the load and store uops are hitting the cache.
Pat

Вверх

Зарегистрируйтесь, чтобы оставить комментарий.