>>>I want to calculate the "Last Level Cache Miss". I use these three events LLC_Misses(0x63412E), LLC_HIT(0x6308D2) and LLC_HITM(0x6304D2). The formula is LLC_Misses/(LLC_Misses+LLC_HIT+LLC_HITM). There are many events about LLC, I don't know the better way to calculate the LLCM.>>>

Do you want to calculate the LLCM ratio programatically by directly accessing MSR registers?In such a case you need to write kernel-mode driver because rdmsr and wrmsr instructions are treated by the cpu as a privileged.
I have a kernel mode driver(very simple) which programatically accesses and reads Uncore PMU CBo counters if you are interested I can post the source code.

>>>My question is the calculation method of LLCM Ratio>>>

What kind of programming manual do you use?Is this "Xeon e5 2600 Uncore programming guide" manual?

>>> It's true that it get evnets by directly accessing MSR registers.>>>
Yes,but you need an adress of specific MSR register, that address is passed in 'ecx' register and the result is returned in 'edx:eax' register pair.
In order to load and/or modify edx:eax you issue 'rdmsr' and 'rdmsr' priviledged ring0 instructions, next you can use and or assemble instruction to mask and set variuos bitfields.I would also recommend you to design your own typedef structures which will represent exactly a MSR register bitfields.
Please be careful during driver testing and runt it only on the test machine.

>>>If could, I want to get the source code. Thanks for your help.>>>

I will share my code, but remember that I was not able to test it because I have not a Xeon CPU.Moreover my driver uses DbgPrint routine to print to the kernel debugger console and you won't be able to see those messages on your Std console output.You need to attach a kernel debugger to your test system or download WinDbgview tool which will intercept and print those messages.
Please ask if you have any questions

Hi GHui!

I'm posting two examples of my source code.First example is simple driver which is elevating KIRQL IRQL and you can use it as a template , please remove only IRQL related routine.
Second example shows how to access MSR registers.Be careful when you run that example because I was not able to test it on Xeon CPU system.

Quote:

GHui wrote:

Quote:

iliyapolak wrote:

>>>My question is the calculation method of LLCM Ratio>>>

What kind of programming manual do you use?Is this "Xeon e5 2600 Uncore programming guide" manual?

Intel® 64 and IA-32 Architectures Software Developer's Manual Combined
The following is download link.
http://www.intel.com/content/www/us/en/processors/architectures-software...

Thank you I will look through the info and follow up with some working examples.

@GHui

Do you know how to set up driver programming environment?

@GHui

Regarding an exact implementation of the Last Level Cache Miss formula , I would use the following approach.
Gather all data from the specific counter(s) which are represented by specific MSR register(s) in the case when only one register is responsible for accessing that data you will need to mask some bitfields.After that save on the stack and/or in the local variables and directly implement this formula "LLC_Misses/(LLC_Misses+LLC_HIT+LLC_HITM)".
For printing the result to the console you are forced to use kernel mode debugger like kd.exe or windbg.exe running in kernel mode.I will suggest you to download Windbgview tool which is nice GUI utillity able to communicate with underlaying driver module and intercept DbgPrint calls.