Sid Meier’s Civilization* series has a successful 20-year history. This white paper describes how Firaxis utilized Intel® GPA to ensure Civilization V (Civ5) offers the best possible mix of graphics & game performance for the vast majority of systems.
Performance analysis
Memory Conflicts in Functional-Decomposition Problems
Challenge
Identify memory conflicts in a functional-decomposition problem to identify data-restructuring requirements. This procedure is part of the design phase for threaded applications that is necessary in order to identify issues that could cause performance degradation.
Isolate Application Performance Issues on Hyper-Threading Technology-Enabled Systems
Challenge
Identify the source of performance degradations or low performance gains of applications running on systems that support Hyper-Threading Technology. Once applications have been tuned for the Pentium® 4 processor, they can be tuned for processors that support Hyper-Threading Technology as a separate process. In some cases, however, the tuning process may not yield acceptable increases in performance.
Using VTune™ Performance Analyzer to Optimize MID Device Performance
Robert Mueller showcases the VTune™ Performance Analyzer usage model for remote data collection on MIDs
Pipeline Speak, Part 2: The Second Part of the Sandy Bridge Pipeline
Last week I posted a blog explaining the front-end of the pipeline on Intel® Microarchitecture Codename Sandy Bridge. Today's blog completes the discussion of the pipeline by explaining the back-end, and then why it's helpful to know this stuff in general.
The Back-End
The Back-End
The Intel® VTune™ Amplifier XE Analysis and Results Interface for Intel® Microarchitecture Codename Sandy Bridge video
This video walks you through using the new Intel® VTune™ Amplifier XE interface and analysis features for Intel® Microarchitecture Codename Sandy Bridge.
Performance Analysis Methodology for Intel® Microarchitecture Codename Sandy Bridge Video
This video explains the tuning methodology we recommend for using Intel® VTune™ Amplifier XE to tune software on Intel® Microarchitecture Codename Sandy Bridge.
Upcoming Webinars on Performance Tuning on Intel® Microarchitecture Codename Sandy Bridge
I will be presenting a 2-part webinar on Nov 8th and 9th on performance tuning on Intel® Microarchitecture Codename Sandy Bridge. The webinars will walk through our Using Intel® VTune™ Amplifier XE on Sandy Bridge tuning guide. In each one I will walk through half of the guide, explaining the concepts and taking live questions.
Detect Stalls Due to Exceeding Write-Combining Store Buffers on Hyper-Threading Technology-Enabled Systems
Challenge
Determine whether performance degradation (or lower-than-expected performance benefit) from Hyper-Threading Technology is due to exceeding the write-combining buffer capacity. A write-combining (WC) store buffer accumulates multiple stores in the same cache line before eventually writing the combined data farther out into the memory hierarchy, to accelerate processor write performance.
What we’ve been doing to make performance analysis easier on Intel® Microarchitecture Codename Sandy Bridge
New Intel® Microarchitecture Codename Sandy Bridge support and tuning guide!
We’ve been listening to your feedback on software tuning. Specifically, we’ve been working to make it even easier for developers to analyze software performance on Intel® Microarchitecture Codename Sandy Bridge.
We’ve been listening to your feedback on software tuning. Specifically, we’ve been working to make it even easier for developers to analyze software performance on Intel® Microarchitecture Codename Sandy Bridge.
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