Pin
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#include "level_base.H"
Classes | |
struct | LEVEL_BASE::REGDEF_ENTRY |
Enumerations | |
enum | LEVEL_BASE::REG { REG_INVALID_ = 0, REG_GR_BASE = REG_RBASE, LEVEL_BASE::REG_RDI = REG_GR_BASE, LEVEL_BASE::REG_GDI = REG_RDI, LEVEL_BASE::REG_RSI, LEVEL_BASE::REG_GSI = REG_RSI, LEVEL_BASE::REG_RBP, LEVEL_BASE::REG_GBP = REG_RBP, LEVEL_BASE::REG_RSP, LEVEL_BASE::REG_STACK_PTR = REG_RSP, LEVEL_BASE::REG_RBX, LEVEL_BASE::REG_GBX = REG_RBX, LEVEL_BASE::REG_RDX, LEVEL_BASE::REG_GDX = REG_RDX, LEVEL_BASE::REG_RCX, LEVEL_BASE::REG_GCX = REG_RCX, LEVEL_BASE::REG_RAX, LEVEL_BASE::REG_GAX = REG_RAX, REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, REG_GR_LAST = REG_R15, REG_SEG_BASE, REG_SEG_CS = REG_SEG_BASE, REG_SEG_SS, REG_SEG_DS, REG_SEG_ES, REG_SEG_FS, REG_SEG_GS, REG_SEG_LAST = REG_SEG_GS, REG_RFLAGS, REG_GFLAGS =REG_RFLAGS, REG_RIP, REG_INST_PTR = REG_RIP, REG_AL, REG_AH, REG_AX, REG_CL, REG_CH, REG_CX, REG_DL, REG_DH, REG_DX, REG_BL, REG_BH, REG_BX, REG_BP, REG_SI, REG_DI, REG_SP, REG_FLAGS, REG_IP, REG_EDI, REG_DIL, REG_ESI, REG_SIL, REG_EBP, REG_BPL, REG_ESP, REG_SPL, REG_EBX, REG_EDX, REG_ECX, REG_EAX, REG_EFLAGS, REG_EIP, REG_R8B, REG_R8W, REG_R8D, REG_R9B, REG_R9W, REG_R9D, REG_R10B, REG_R10W, REG_R10D, REG_R11B, REG_R11W, REG_R11D, REG_R12B, REG_R12W, REG_R12D, REG_R13B, REG_R13W, REG_R13D, REG_R14B, REG_R14W, REG_R14D, REG_R15B, REG_R15W, REG_R15D, REG_MM_BASE, REG_MM0 = REG_MM_BASE, REG_MM1, REG_MM2, REG_MM3, REG_MM4, REG_MM5, REG_MM6, REG_MM7, REG_MM_LAST = REG_MM7, REG_XMM_BASE, REG_FIRST_FP_REG = REG_XMM_BASE, REG_XMM0 = REG_XMM_BASE, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7, REG_XMM8, REG_XMM9, REG_XMM10, REG_XMM11, REG_XMM12, REG_XMM13, REG_XMM14, REG_XMM15, REG_XMM_SSE_LAST = REG_XMM15, REG_XMM_AVX_LAST = REG_XMM_SSE_LAST, REG_XMM_AVX512_HI16_FIRST, REG_XMM16 = REG_XMM_AVX512_HI16_FIRST, REG_XMM17, REG_XMM18, REG_XMM19, REG_XMM20, REG_XMM21, REG_XMM22, REG_XMM23, REG_XMM24, REG_XMM25, REG_XMM26, REG_XMM27, REG_XMM28, REG_XMM29, REG_XMM30, REG_XMM31, REG_XMM_AVX512_HI16_LAST = REG_XMM31, REG_XMM_AVX512_LAST = REG_XMM_AVX512_HI16_LAST, REG_XMM_LAST = REG_XMM_AVX512_LAST, REG_YMM_BASE, REG_YMM0 = REG_YMM_BASE, REG_YMM1, REG_YMM2, REG_YMM3, REG_YMM4, REG_YMM5, REG_YMM6, REG_YMM7, REG_YMM8, REG_YMM9, REG_YMM10, REG_YMM11, REG_YMM12, REG_YMM13, REG_YMM14, REG_YMM15, REG_YMM_AVX_LAST = REG_YMM15, REG_YMM_AVX512_HI16_FIRST, REG_YMM16 = REG_YMM_AVX512_HI16_FIRST, REG_YMM17, REG_YMM18, REG_YMM19, REG_YMM20, REG_YMM21, REG_YMM22, REG_YMM23, REG_YMM24, REG_YMM25, REG_YMM26, REG_YMM27, REG_YMM28, REG_YMM29, REG_YMM30, REG_YMM31, REG_YMM_AVX512_HI16_LAST = REG_YMM31, REG_YMM_AVX512_LAST = REG_YMM_AVX512_HI16_LAST, REG_YMM_LAST = REG_YMM_AVX512_LAST, REG_ZMM_BASE, REG_ZMM0 = REG_ZMM_BASE, REG_ZMM1, REG_ZMM2, REG_ZMM3, REG_ZMM4, REG_ZMM5, REG_ZMM6, REG_ZMM7, REG_ZMM8, REG_ZMM9, REG_ZMM10, REG_ZMM11, REG_ZMM12, REG_ZMM13, REG_ZMM14, REG_ZMM15, REG_ZMM_AVX512_SPLIT_LAST = REG_ZMM15, REG_ZMM_AVX512_HI16_FIRST, REG_ZMM16 = REG_ZMM_AVX512_HI16_FIRST, REG_ZMM17, REG_ZMM18, REG_ZMM19, REG_ZMM20, REG_ZMM21, REG_ZMM22, REG_ZMM23, REG_ZMM24, REG_ZMM25, REG_ZMM26, REG_ZMM27, REG_ZMM28, REG_ZMM29, REG_ZMM30, REG_ZMM31, REG_ZMM_AVX512_HI16_LAST = REG_ZMM31, REG_ZMM_AVX512_LAST = REG_ZMM_AVX512_HI16_LAST, REG_ZMM_LAST = REG_ZMM_AVX512_LAST, REG_K_BASE, REG_K0 = REG_K_BASE, REG_IMPLICIT_FULL_MASK = REG_K0, REG_K1, REG_K2, REG_K3, REG_K4, REG_K5, REG_K6, REG_K7, REG_K_LAST = REG_K7, REG_MXCSR, REG_MXCSRMASK, REG_ORIG_RAX, REG_ORIG_GAX = REG_ORIG_RAX, REG_FPST_BASE, REG_FPSTATUS_BASE = REG_FPST_BASE, REG_FPCW = REG_FPSTATUS_BASE, REG_FPSW, LEVEL_BASE::REG_FPTAG, REG_FPIP_OFF, REG_FPIP_SEL, REG_FPOPCODE, REG_FPDP_OFF, REG_FPDP_SEL, REG_FPSTATUS_LAST = REG_FPDP_SEL, LEVEL_BASE::REG_FPTAG_FULL, REG_ST_BASE, REG_ST0 = REG_ST_BASE, REG_ST1, REG_ST2, REG_ST3, REG_ST4, REG_ST5, REG_ST6, REG_ST7, REG_ST_LAST = REG_ST7, REG_FPST_LAST = REG_ST_LAST, REG_DR_BASE, REG_DR0 = REG_DR_BASE, REG_DR1, REG_DR2, REG_DR3, REG_DR4, REG_DR5, REG_DR6, REG_DR7, REG_DR_LAST = REG_DR7, REG_CR_BASE, REG_CR0 = REG_CR_BASE, REG_CR1, REG_CR2, REG_CR3, REG_CR4, REG_CR_LAST = REG_CR4, REG_TSSR, REG_LDTR, REG_TR_BASE, REG_TR = REG_TR_BASE, REG_TR3, REG_TR4, REG_TR5, REG_TR6, REG_TR7, REG_TR_LAST = REG_TR7, LEVEL_BASE::REG_SEG_GS_BASE = REG_TOOL_BASE, LEVEL_BASE::REG_SEG_FS_BASE, REG_INST_BASE, LEVEL_BASE::REG_INST_SCRATCH_BASE = REG_INST_BASE, LEVEL_BASE::REG_INST_G0 = REG_INST_SCRATCH_BASE, LEVEL_BASE::REG_INST_G1, LEVEL_BASE::REG_INST_G2, LEVEL_BASE::REG_INST_G3, LEVEL_BASE::REG_INST_G4, LEVEL_BASE::REG_INST_G5, LEVEL_BASE::REG_INST_G6, LEVEL_BASE::REG_INST_G7, LEVEL_BASE::REG_INST_G8, LEVEL_BASE::REG_INST_G9, LEVEL_BASE::REG_INST_G10, LEVEL_BASE::REG_INST_G11, LEVEL_BASE::REG_INST_G12, LEVEL_BASE::REG_INST_G13, LEVEL_BASE::REG_INST_G14, LEVEL_BASE::REG_INST_G15, LEVEL_BASE::REG_INST_G16, LEVEL_BASE::REG_INST_G17, LEVEL_BASE::REG_INST_G18, LEVEL_BASE::REG_INST_G19, LEVEL_BASE::REG_INST_G20, LEVEL_BASE::REG_INST_G21, LEVEL_BASE::REG_INST_G22, LEVEL_BASE::REG_INST_G23, LEVEL_BASE::REG_INST_G24, LEVEL_BASE::REG_INST_G25, LEVEL_BASE::REG_INST_G26, LEVEL_BASE::REG_INST_G27, LEVEL_BASE::REG_INST_G28, LEVEL_BASE::REG_INST_G29, REG_INST_TOOL_FIRST = REG_INST_G0, REG_INST_TOOL_LAST = REG_INST_G29, REG_BUF_BASE0, REG_BUF_BASE1, REG_BUF_BASE2, REG_BUF_BASE3, REG_BUF_BASE4, REG_BUF_BASE5, REG_BUF_BASE6, REG_BUF_BASE7, REG_BUF_BASE8, REG_BUF_BASE9, REG_BUF_BASE_LAST = REG_BUF_BASE9, REG_BUF_END0, REG_BUF_END1, REG_BUF_END2, REG_BUF_END3, REG_BUF_END4, REG_BUF_END5, REG_BUF_END6, REG_BUF_END7, REG_BUF_END8, REG_BUF_END9, REG_BUF_ENDLAST = REG_BUF_END9, REG_BUF_LAST = REG_BUF_ENDLAST, REG_INST_SCRATCH_LAST = REG_BUF_LAST, LEVEL_BASE::REG_INST_G0D, LEVEL_BASE::REG_INST_G1D, LEVEL_BASE::REG_INST_G2D, LEVEL_BASE::REG_INST_G3D, LEVEL_BASE::REG_INST_G4D, LEVEL_BASE::REG_INST_G5D, LEVEL_BASE::REG_INST_G6D, LEVEL_BASE::REG_INST_G7D, LEVEL_BASE::REG_INST_G8D, LEVEL_BASE::REG_INST_G9D, LEVEL_BASE::REG_INST_G10D, LEVEL_BASE::REG_INST_G11D, LEVEL_BASE::REG_INST_G12D, LEVEL_BASE::REG_INST_G13D, LEVEL_BASE::REG_INST_G14D, LEVEL_BASE::REG_INST_G15D, LEVEL_BASE::REG_INST_G16D, LEVEL_BASE::REG_INST_G17D, LEVEL_BASE::REG_INST_G18D, LEVEL_BASE::REG_INST_G19D, LEVEL_BASE::REG_INST_G20D, LEVEL_BASE::REG_INST_G21D, LEVEL_BASE::REG_INST_G22D, LEVEL_BASE::REG_INST_G23D, LEVEL_BASE::REG_INST_G24D, LEVEL_BASE::REG_INST_G25D, LEVEL_BASE::REG_INST_G26D, LEVEL_BASE::REG_INST_G27D, LEVEL_BASE::REG_INST_G28D, LEVEL_BASE::REG_INST_G29D, REG_TOOL_LAST = REG_INST_G29D, REG_LAST } |
enum | LEVEL_BASE::REG_ACCESS { REG_ACCESS_READ, REG_ACCESS_WRITE, REG_ACCESS_OVERWRITE } |
enum | LEVEL_BASE::REGNAME { REGNAME_LAST } |
Variables | |
const REGDEF_ENTRY | LEVEL_BASE::_regDefTable [] |
UINT64 | LEVEL_BASE::_regClassBitMapTable [REG_LAST] |
UINT64 | LEVEL_BASE::_regSubClassBitMapTable [REG_LAST] |
UINT32 | LEVEL_BASE::_regSpillSizeTable [REG_LAST] |
REGWIDTH | LEVEL_BASE::_regWidthTable [REG_LAST] |
REG_ALLOC_TYPE | LEVEL_BASE::_regAllocTypeTable [REG_LAST] |
REG | LEVEL_BASE::_regFullNameTable [REG_LAST] |
REG | LEVEL_BASE::_regMachineNameTable [REG_LAST] |
REG | LEVEL_BASE::_regPinNameTable [REG_LAST] |
INT32 | LEVEL_BASE::_regWidthToBitWidth [] |
This file contains REG primitives