I am trying to write a simple assembly code in asm using the AVX instructions. I have seen a problem rising up while adding large numbers. The code is here:

__asm__ __volatile__(
"vzeroall\n\t"
"movl $0, %%r9d\n\t"
"movl $4, %%r10d\n\t"
"leal (%%eax, %%r9d, 1), %%edx\n\t"
"vbroadcastss (%%edx), %%ymm0\n\t"
"leal (%%eax, %%r10d, 1), %%edx\n\t"
"vmovups (%%edx), %%ymm1\n\t"
"vaddps %%ymm0, %%ymm1, %%ymm2\n\t"
"vmovups %%ymm2, (%%edx)"
: "=a"(x) : "a"(x));

I'll be interested to have information about the behavior of prefetch hints instructions such as prefetcht0,prefetchnta,prefetchw,... for modern processors such as Sandy Bridge and Ivy Bridge. I ask because there is nothing about it in the optimization guide [1] apparently. It will be arguably a good thing for developers to know to which cache level data are prefetched with the diverse variants. I'll glad if someone provide a pointer to some detailed explanation.

[1] Intel® 64 and IA-32 Architectures Optimization Reference Manual, Order Number: 248966-026, April 2012

I have the following problem:

Say, at location 'A', I have: c1 d1 c3 d3, which are all doubles (64-bit). I want to fill two registers, a00 and a01 with:

a00-> |d1|c1|d1|c1| ; a01-> |d3|c3|d3|c3|

i.e I want to broadcast the first two elements to register a00 and the next two elements to register a01.

Currently, I'm doing it as follows:

Hi, 

I have a large loop which executes the following piece of code many times: 

-------------------------------------------------------------------------

//input: _m128d U_c00, U_c01, U_c02, U_c10, U_c11, U_c12, U_c20, U_c21, U_c22, psi_c0, psi_c1, psi_c2;

//output: _m128d chi_c0, chi_c1, chi_c2;