Intel® Many Integrated Core Architecture (Intel MIC Architecture)

mic bandwidth

Hi All,

      I am writing an application on MIC architecture,  I want to know the theorical bandwith between each memory device.

Like bandwidth between core and L1, L1 and L2, L2 and memory.  I want these information to evaluate my application.

So I want to know how many Load can be issued each clock cycle. ? 

How many cycles needed to translate a 64byte cache line from L2 to L1 ?

I want to know the theorical value  regardless of  application?

Thank  you ~

Using -mmic in cross compilation on RHEL5.2

We use an x86_64 RHEL5.2 build platform. Can I build (Recompile the GPL Binaries from Source) the MPSS on this platform, then run my build using -mmic flag during compilation, and produce output that will run on other systems, such as RHEL6.3 or SLES 11 SP2? 

The MPSS doc refers only to RH 6.0 and SLES 11 SP1 and above, but I only need to be able to build on RH5.2, not run the output.

offload error: cannot get device 0 handle (error code 2)

Hello ,

I have a setup of 2 MIC cards on one node, if lets say MIC 0 is not up while MIC 1 is up, Then on executing code, it gives me following error.

      offload error: cannot get device 0 handle (error code 2).

     On offload statement like this  :

      #pragma offload target(mic:-1) inout(a : length(size) alloc_if(1) free_if(0)) in(size)

      OR 

        #pragma offload target(mic:1) inout(a : length(size) alloc_if(1) free_if(0)) in(size)

PHI w/ MPICH (3.0.3) ch3:nemesis:scif

I'm trying to get MPICH (3.0.3) and SCIF working.

I'm using the tests from osu_benchmarks(from mvapich2 tarball) as a set of sanity checks, and I'm running into some unexpected errors.

One example: running osu_mbw_mr works sometimes, and then fail on the next try. The printout from two successive runs as well as the hosts file are below.
Compiler is latest (13.1.1) icc; latest MPSS (2-2.1.5889-14); Centos 6.4.

SCIF connection refused

For some reason the SCIF interface in my compute nodes is refusing connections. Any ideas on what's wrong or where to start investigating:

The node has a Mellanox ConnectX-3 HCA with the latest Gold Update 2 MPSS and everything else set up "by the book". All the IB services and modules load nicely and seem to work and I can ssh into the MIC and run natively.

However, if I try to run an offload (LEO or OpenCL) application it hangs. Doing an strace reveals the following:

Kernel Panic on MIC boot

After an upgrade of a node from MPSS Gold Update 1 to Update 2 I have had issues with the frontend node in our cluster crashing on boot. I tried to downgrade back to Update 1 but it still keeps happening.

We have upgraded the compute nodes succesfully. They have identical hardware and a bridged network configuration. The frontend has the default configuration in /etc/sysconfig/mic.

The host OS is CentOS 6.3 and the card model is 5110P (B1)

On the host side we get the  following error during boot:

On compilation getting rpath error

Hello,

I am writing this test code :

#include <stdio.h>

#include "offload.h"

int main()
{
char cdir[128];
int ndevices, devnum;

getcwd(cdir,sizeof(cdir));
ndevices = _Offload_number_of_devices();
devnum = _Offload_get_device_number();
printf("\n Hello...%s %d %d \n",cdir,ndevices,devnum);
return 0;
}

and compiling 

icc -o hello hello.c -loffload

compiles succesfully

However, when i am compiling as 

icc -o hello hello.c -loffload -mmic

MIC performance-single threaded

To get a better idea of MIC's single core, single threaded performance, I tried the following simple experiment:

The following is a simple, unvectorized code, where I take two vectors "arr1" and "arr2" of length=LENGTH and multiply them their corresponding elements with each other, LOOP number of times. I have kept LENGTH short enough so that both vectors fit in the L1 cache, so this shouldn't be memory bound. For ex: LOOP = 1000000 and LENGTH < 256 (should fit within L1 cache).

I compiled without using any optimization flags.

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