fsycl-link

Tells the compiler to perform a partial link of device binaries to be used with Flexible Programmable Gate Array (FPGA).

Syntax

Linux:

-fsycl-link[=value]

Windows:

-fsycl-link[=value]

Arguments

value

Can be one of the following:

early

Tells the compiler to generate an html report when the partial link is created. This lets you check the program if need be.

You can resume from this point and generate an FPGA image by specifying option -fintelfpga with the generated binary.

image

Tells the compiler to generate an FPGA bitstream. It will then be ready to be linked and used on a FPGA board.

image takes much longer to generate than does early.

Default

OFF

No partial link of device binaries is performed.

Description

This option tells the compiler to perform a partial link of device binaries to be used with Flexible Programmable Gate Array (FPGA).

This partial link is then wrapped by the offload wrapper, allowing the device binaries to be linked by the host compiler or linker.

If you do not specify a value, the following occurs:

IDE Equivalent

None

Alternate Options

None

See Also