Processors Affected: Microarchitectural Data Sampling

For more information on microarchitectural data sampling (MDS) refer to the MDS disclosure and Intel Analysis of Microarchitectural Data Sampling.

CPUID.(EAX=7H,ECX=0):EDX[MD_CLEAR=10] enumerates support for additional functionality that will flush microarchitectural structures as listed below.

1. On execution of the (existing) VERW instruction where its argument is a memory operand.
2. On setting the L1D_FLUSH command (on processors that enumerate both CPUID.(EAX=7H,ECX=0):EDX[MD_CLEAR=10] and CPUID.(EAX=7H,ECX=0):EDX[L1D_FLUSH=28] bit in the IA32_FLUSH_CMD MSR).
3. On execution of the RSM instruction.
4. On entry to, or exit from an Intel® Software Guard Extensions (Intel® SGX) enclave.

The following MSR enumeration enables software to check if the processor is affected by MDS methods:

A value of 1 indicates that the processor is not affected by RDCL or L1TF. In addition, a value of 1 indicates that the processor is not affected by MFBDS.

• IA32_ARCH_CAPABILTIES[0]: RDCL_NO
• IA32_ARCH_CAPABILITIES[5]: MDS_NO

  A value of 1 indicates that processor is not affected by MFBDS/MSBDS/MLPDS/MDSUM.

Note that MFBDS is mitigated if either the RDCL_NO or MDS_NO bit (or both) are set. Some existing processors may also enumerate either RDCL_NO or MDS_NO only after a microcode update is loaded.

Note Future processors set the MDS_NO bit in IA32_ARCH_CAPABILITIES to indicate they are not affected by microarchitectural data sampling. Such processors will continue to enumerate the MD_CLEAR bit in CPUID. As none of these data buffers are vulnerable to exposure on such parts, no data buffer overwriting is required or expected for such parts, despite the MD_CLEAR indication. Software should look to the MDS_NO bit to determine whether buffer overwriting mitigations are required.

Note Processors that are not explicitly listed in this table, like processors based on Itanium® microarchitecture, are not affected by MDS.

Note For Intel® SGX, the MD_CLEAR and MDS_NO bits are also indirectly reflected in the Intel SGX Remote Attestation data.

Note All processors affected by MSBDS, MFBDS, or MLPDS are also affected by MDSUM for the relevant buffers. For example, a processor that is only affected by MSBDS but is not affected by MFBDS or MLPDS would also be affected by MDSUM for store buffer entries only.

Intel expects the following products are potentially affected by microarchitectural data sampling issues. For affected steppings cross-check against the list of updated microcode versions.

Table 6. List of MDS-affected processors by Family/Model

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