Flow Graph Analyzer

Visualize Parallelism Graphically represent and analyze your application’s critical path performance. Starting with a blank canvas, construct a flow graph application by interactively adding nodes and edges through a graphical interface.

Model Graphs in a Heterogeneous World

Flow Graph Analyzer (FGA) is a rapid visual prototyping environment. Any developer with Intel® Threading Building Blocks (Intel® TBB) flow graph applications or applications that can be expressed as flow graphs can benefit from this tool.

It assists developers with analyzing and designing parallel applications that use the Intel TBB flow graph interface.

  • Speed up algorithm design and express parallelism efficiently
  • Plan, validate, and model application design and performance before generating Intel TBB code
  • Create parallel applications that take advantage of multicore and heterogeneous systems
  • Pinpoint your performance tuning efforts by using the critical path analysis to reduce the set of nodes (even large graphs) to focus on

User Guide

Design Workflow

Create Intel TBB flow graph diagrams and generate C++ stubs as a starting point for further development. Employ a drag-and-drop paradigm for interactively constructing Intel TBB graphs.

Modeling Workflow

The technical preview feature is available in limited capacity and only supports dependency graphs. Use this workflow between the design and analysis steps to project the scalability of a dependency graph and iteratively refine the graph topology to maximize scalable performance.

Analyzer Workflow

Collect and visualize execution traces from Intel TBB flow graph applications. From FGA, you can explore the topology of your graphs, interact with a timeline of node executions, and project important statistics onto graph nodes.

Learn About Additional Features

Roofline Analysis

Optimize your application for memory and compute.

Vectorization Optimization

Enable more vector parallelism and improve its efficiency.

Thread Prototyping

Model, tune, and test multiple threading designs.



英特尔的编译器针对非英特尔微处理器的优化程度可能与英特尔微处理器相同(或不同)。这些优化包括 SSE2、SSE3 和 SSSE3 指令集和其他优化。对于在非英特尔制造的微处理器上进行的优化,英特尔不对相应的可用性、功能或有效性提供担保。该产品中依赖于微处理器的优化仅适用于英特尔微处理器。某些非特定于英特尔微架构的优化保留用于英特尔微处理器。关于此通知涵盖的特定指令集的更多信息,请参阅适用产品的用户指南和参考指南。

通知版本 #20110804