OpenMP and Win32 Threads Usage Example
by Stanislav Bratanov
The code example computes a trigonometric formula for arrays of input coefficients and parallels the computation either using OpenMP directives or creating threads manually. The performance of both approaches is measured and compared.
MPI Parallelizes Work among Multiple Processors or Hosts
by John Sharp, Content Master Ltd
Message passing is a common technique for performing parallel processing spread among multiple processors. Processes execute tasks on individual processors and communicate with each other by sending messages. In this way, processes can operate in a semi-autonomous manner, performing distinct computations that form part of a larger job, sharing data and synchronizing with each other when required.
Detecting Multi-Core Processor Topology in an IA-32 Platform
by Khang Nguyen and Shihjong Kuo
This paper discusses a robust algorithm to help application software enumerate the processor and cache topology in any single or multi-processor platform, using Intel processors. Enumerating processor topology correctly is essential for implementing licensing policy requirements. Understanding processor and cache topology information allows multithreading software to make more efficient use of hardware multithreading resources and deliver optimal performance.
Utilizing Thread Pools in Performance-Critical Applications
Basic OpenMP Threading Overhead
This code takes a simple piece of serial code and threads it several different ways. It uses a test harness to measure this, and helps us understand the differences between the various methods.
Threaded Cross-Platform Game Development
Source code here
Intel® Tools Make Threading Easier on Multiple Processors
Intel® Thread Profiler, Intel® Thread Checker, and the Intel® Compiler with Support for OpenMP* Allow Quick Performance Estimation for Threading Applications.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804