Analysis and Optimization of Financial Analytics Benchmark on Modern Multi- and Many-core IA-Based Architectures

By Belinda M Liviero, Published: 10/15/2013, Last Updated: 10/15/2013

By Mikhail Smelyanskiy, Jason Sewall, Dhiraj D. Kalamkar, Nadathur Satish, Pradeep Dubey, Nikita Astafiev, Ilya Burylov, Andrey Nikolaev, Sergey Maidanov, Shuo Li, Sunil Kulkarni, Charles H. Finan, Ekaterina Gonina

Abstract

In the past 20 years, computerization has driven explosive growth in the volume of financial markets and in the variety of traded financial instruments. Increasingly sophisticated mathematical and statistical methods and rapidly expanding computational power to drive them have given rise to the field of computational finance. The wide applicability of these models, their computational intensity, and their real-time constraints require high-throughput parallel architectures.

In this work, we have assembled a financial analytics workload for derivative pricing, an important area of computational finance. We characterize and compare our workload’s performance on two modern, parallel architectures: the Intel® Xeon® Processor E5-2680, and the recently announced Intel® Xeon Phi™ (formerly codenamed ‘Knights Corner’) coprocessor. In addition to analysis of the peak performance of the workloads on each architecture, we also quantify the impact of several levels of compiler and algorithmic optimization.

Overall, we find that large caches on both architectures, out-oforder cores on Intel® Xeon® processor, and large compute and memory bandwidth on Intel® Xeon Phi™ coprocessor deliver high level of performance on financial analytics.

Read the PDF Analysis and Optimization of Financial Analytics Benchmark on Modern Multi- and Many-core IA-Based Architectures

Additional Resources

Intel® Xeon Phi™ Coprocessor Developer zone

Intel® Many Integrated Core Architecture Forum

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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