Code and Data Prioritization Proof Points and Software Enabling

By Khang T Nguyen, Published: 02/11/2016, Last Updated: 02/11/2016


The Code and Data Prioritization (CDP) feature, as described in the previous article in this series, provides software-programmable control of code and data placement in the last-level cache (LLC). This enables isolation of code from data in cases where an application may have a large or streaming data footprint, for instance.

Software Support

Several software packages support CDP, including the Linux* kernel, KVM, and the RDT Utility posted at specifically:

  • Linux kernel: The Linux kernel support for Cache Allocation Technology (CAT) also includes CDP. The latest patches are available here:
  • KVM: The KVM hypervisor is supported as part of the Linux kernel enabling.
  • Xen: The Xen Hypervisor is planning to support CDP in version 4.7.
  • RDT Utility: The RDT Utility at (Overview, GitHub*) provides support for all of the RDT features, including CDP. Command-line flags are provided to enable/disable and configure the feature, and the code is provided under the commercial-friendly BSD license.

Support for additional software is pending.

Proof Points

Example data showing the benefits of CDP will be published when available. Example benefits have been shown across a number of applications.


The CDP feature enables software control over code and data fills on the LLC, providing further software control for specialized use cases. Initial software support is described above and full documentation is available in the Intel Software Developer Manuals.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804