Intel’s Pre-Silicon Customer Acceleration (PCA) program scales innovation across all operating environments using the Simics® virtual platform as a primary technology. The program helps customers develop, test, tune, and optimize mission-critical code, including operating systems, BIOS, and firmware, before silicon is ready—shifting those efforts earlier (to the left) in customers’ product development cycles. The business result is faster time-to-market (TTM) for hardware and software developers across the Intel ecosystem.
For Intel’s customers to achieve faster product releases, new and complex features in Intel® silicon need a software development runway. In addition, Intel needs close collaboration and feedback on the system software we deliver to customers. Intel’s Pre-Silicon Customer Acceleration (PCA) program accomplishes those goals as it aims to enable each mission-critical software stack to boot and run on Day 1 at customer platform power-on, significantly reducing customer time-to-launch.
Our customers face time-to-market (TTM) challenges as they contend with increased hardware complexity, competitive pressure, software/hardware integration, and initially limited hardware availability. The PCA program speeds-up TTM by driving parallelization of each customer’s software development process with Intel’s own product development.
That effort requires the PCA team to engage early in Intel’s own development process to understand and incorporate customer requirements, upfront. Primary deliveries to customers take place between nine months to a year ahead of first silicon samples and continue throughout the development process.
The PCA program supports dozens of original equipment manufacturers (OEMs) and original device manufacturers (ODMs), along with major independent firmware vendors (IFVs), operating system vendors (OSVs), and independent software vendors (ISVs). The PCA team also partners with electronic design automation (EDA) houses to support more sophisticated solutions at customer sites.
By supporting IFVs, OSVs and others that deliver to our customers, we help complete early readiness of the entire software stack. The PCA team focuses on ensuring each customer’s system software is ready. That includes layers such as:
The Simics virtual platform (VP) is the primary solution the PCA team uses to represent Intel’s silicon well ahead of its actual arrival. Each VP model is register-accurate, allowing customers to develop their system and platform software on top. That allows for a smooth transition to hardware. Customers continue to use this developer-friendly VP environment for software development, continuous integration, and testing, even after silicon arrives.
Hewlett Packard Enterprise (HPE) is an industry leader in servers, storage, wired and wireless networking, converged systems, software, services and cloud. As one of the top customers for Intel’s Data Center Group, HPE relies on Simics VP software for their BIOS/firmware development, continuous integration, and regression testing.
“Server market dynamics are changing quickly, and we need to react with new products faster than ever,” says HPE Senior Firmware Development Manager, James Bodner. “Not hitting a TTM launch costs in lost revenue, and firmware complexity has become the leading driver of program schedules.” Together with challenges in getting early silicon in volume, those issues drive HPE’s need to do more pre-silicon.
According to Bodner, the heart of HPE innovation and server products is the HPE Integrated Lights-Out (iLO) Baseboard Management Controller (BMC). It represents 20 Years of HPE value add, and HPE has accumulated 20 years of dependencies between BIOS and the iLO BMC. HPE and Intel collaborated on how the model could be built for this effort.
“We started laying out a framework a year ago. The first-generation goal in 2018 was to get a basic model, but it still required significant firmware work,” says Bodner. “We’re extending the model interfaces to include the HPE non-volatile memory store, and we’re on-track to get to a fully functional iLO model running BMC firmware and BIOS, using real firmware with no modifications.”
Bodner added that HPE already had its own simulation environment with millions of lines of code already written. “To avoid starting over from scratch, HPE ASIC developers came up with a way to translate the HPE simulation model to Simics, greatly accelerating the effort. We’re already booting Intel’s next-generation ‘Whitley’ platform to Linux* on a Simics VP with the iLO model, using the HPE BIOS. We have a global team of more than 20 developers actively using the Simics VP to develop and test changes, and we’ve ported and tested 200+ changes to Whitley reference code.”
Some recent HPE power-on successes with Simics VP software include:
“These milestones represent significant improvement from previous generation power-on events: from days to hours!” says Bodner. “Our future initiatives include tying Simics into HPE’s continuous integration framework, to ensure every change is tested before it is committed, and to improve quality by finding issues before they get into source control—to stop the problem before it is released.”
American Megatrends International LLC (AMI) is the world's leading provider of BIOS and UEFI firmware and out-of-band server management solutions. AMI CEO Sanjoy Maity shared his thoughts on the synergy between Intel Simics initiatives and AMI’s vision.
“AMI has been using Simics for a few generations of Intel silicon,” says Maity. “AMI enables customers with Simics boot as soon as it is available from Intel. That enables customers to adapt their IP to the new project codebase.”
Maity listed several ways that AMI uses Simics VPs:
“Simics is the perfect companion for today’s ‘Agile Development Model’ because it brings higher efficiency, better visibility, and adaptability,” Maity adds. “We use it for delivery and continuous integration.”
Maity points out that increasing efficiency in development requires AMI to do three things: increasing access to the hardware; collaborative development; and automating development through DevOps. “This means build more hardware at an earlier stage, which could result in a ridiculously high investment in hardware.”
Simics VPs solve that problem for AMI in four ways, he says:
“However, Simics has much broader potential beyond just silicon modeling,” Maity observes. “Simics can help in full server product development. It can extend simulations to all silicon features, and the ecosystem can benefit from full platform simulation. Simics can be instrumental to shorten time-to-market. So, the sky is the limit! Simics can shift left the entire ecosystem.”
The next steps envisioned by Maity include working with Intel as an ecosystem partner and working with OEMs and ODMs on Simics-enabled platform development. “The goal would be to help simulate end-user deployment scenarios and help triage issues that are difficult to reproduce on physical hardware. This would enable cloud and hyperscale customers to reduce complex hardware dependencies, and it would help OEMs and ODMs to adopt and heavily use Simics for development, validation and support.”
Simics enables developers to simulate anything, chip to system, and get the access, automation, and collaboration tools required for Agile development practices.
Shifting Left—Building Systems & Software before Hardware Lands: Our shift-left began with efforts to coordinate the co-development of platform hardware and software—one effect was moving software from the end of product development to front and center.
Additional Notes about Temporal Decoupling: Temporal decoupling is a key technology in virtual platforms—it can speed up the execution of a system by several orders of magnitude.
The More the Merrier – Building Virtual Platforms for Integration: To do integration pre-silicon, we need virtual platforms that provide a complete system setup: from the main cores running the main software stacks, to processor cores inside the IP blocks that run firmware.
Michael Greene is Intel Vice President and General Manager of System Technologies & Optimization in the Intel Architecture, Graphics and Software organization. Greene leads a worldwide division responsible for a broad range of development, validation, enabling, and architecture analysis efforts for Intel platforms, including pre-silicon software, virtual platforms modeling and simulation solutions, and power performance analysis, to increase development velocity and time to market. Greene joined Intel in 1990, after graduating from the Massachusetts Institute of Technology and has managed several new product developments, research efforts, and engineering groups. He has served as Intel’s initiative owner for power efficiency, pre-silicon software readiness, and has driven new technology benchmarking throughout his career. Greene is also Chairman of the Board for the National GEM Consortium. GEM is a national non-profit providing programming and full fellowships to support the number of under-represented individuals who pursue a master’s or doctorate degree in science or engineering. Follow Michael on Twitter.
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