Explore DPC++ Through Intel® FPGA Code Samples

Version:2021.2   Last Updated:04/27/2021


This guide aims to help you understand the following:

  • How to navigate the Intel® FPGA DPC++ code samples in a coherent manner that builds on complexity and use-case. 
  • How to get your first oneAPI application on the FPGA with the help of six essential FPGA code samples.

To aid you in your learning and to help you navigate through the DPC++ FPGA tutorials folders, use the following dependency diagram, which illustrates the dependencies between the tutorials:

NOTE:  The Intel® oneAPI DPC++ FPGA Optimization Guide, Chapter 1: Introduction To FPGA Design Concepts covers fundamental FPGA concepts, and it is a prerequisite for all FPGA-specific code samples

Intel oneAPI FPGA Code Samples Dependency Diagram


Build and Run a Sample Project

To compile the FPGA tutorials, you must either download and install the Intel® oneAPI Base Toolkit and the Intel® FPGA Add-on for oneAPI Base Toolkit, or have an account on the Intel® DevCloud for oneAPI. 

Refer to the following links to get started with the Intel® oneAPI Base Toolkit guide via the command-line interface (CLI) or integrated development environment (IDE):

Essential FPGA Code Samples

The following FPGA samples represent a selection of useful tutorials suitable to get you started on your first oneAPI application on the FPGA: 

Sample 1: FPGA Compile Flow

This sample introduces the most commonly used compilation flow targeting Intel® FPGA devices and describes when to use each flow.

CLI or IDE Sample Name Link to the Git Repository
fpga_compile FPGA Compile sample

The following flows are described in the sample:

Flow Type Action
Emulation flow to verify functional correctness Compile to verify the program on the CPU emulator.
RTL flow to view the optimization report Stop early in the process of FPGA synthesis to analyze performance bottlenecks of your design with a short turnaround time.
Hardware generation flow to generate an FPGA bitstream Generate an FPGA hardware bitstream and link against the host (CPU) program.

​Key concepts covered in this sample: 

  • How and why compiling DPC++ to FPGA differs from CPU and GPU
  • FPGA device image types and when to use them
  • Compile flags used to target FPGA

Sample 2: Save Development Time

This sample demonstrates how to use the device link mechanism in your FPGA compilation flow to save development time.

CLI or IDE Sample Name Link to the Git Repository
fast_recompile Fast Recompile sample 

Intel® oneAPI DPC++/C++ Compiler supports only the ahead-of-time compilation for FPGA, which means that an FPGA device image is generated at compile time. FPGA device image generation process can take hours to complete. Therefore, if the host and device code are compiled together and a change in the host code is made, the entire source code is subject to this time-consuming process.

The device link mechanism allows you to separate device code compilation and host code compilation. When the code change applies only to host-only files, an FPGA device image is not regenerated, and the lengthy compile time is avoided.

Key concepts covered in this sample: 

  • Why you should separate host and device code compilation in your FPGA project
  • How to use the -reuse-exe flag and device link methods
  • Which method to choose for your project

Sample 3: Avoid Aliasing of Kernel Arguments

This sample demonstrates the use of the DPC++ [[intel::kernel_args_restrict]] kernel attribute, which you can apply when you can guarantee that kernel arguments do not alias (similar to restrict in C++).

CLI or IDE Sample Name Link to the Git Repository
kernel_args_restrict Kernel Arguments Restrict sample

Pointer aliasing occurs when the same memory location is accessed using different names (i.e., variables). Due to pointer aliasing, the compiler must be conservative about optimizations that reorder, parallelize, or overlap operations, which could alias. Using the kernel_args_restrict attribute enables more aggressive compiler optimizations and often improves kernel performance on FPGA. 

Key concepts covered in this sample: 

  • The problem of pointer aliasing and its impact on compiler optimizations
  • The behavior of the kernel_args_restrict attribute and when to use it on your kernel
  • The effect this attribute can have on your kernel's performance on FPGA

Sample 4: Optimize by Improving Loop Throughput 

This sample demonstrates a simple example of unrolling loops to improve the throughput of a DPC++ FPGA program.

CLI or IDE Sample Name Link to the Git Repository
loop_unroll Loop Unroll sample

Loop unrolling is a mechanism to increase program parallelism by duplicating the compute logic within a loop, which allows you to increase your design's throughput.

Key concepts covered in this sample:

  • Basics of loop unrolling
  • Unrolling loops in your program
  • Determining the correct unroll factor for your program

Sample 5: Transfer Data with Pipes

This sample demonstrates how to transfer data between kernels using the pipes abstraction. 

CLI or IDE Sample Name Link to the Git Repository
pipes Pipes sample

Key concepts covered in this sample: 

  • The basics of the FPGA-specific DPC++ pipes extension
  • How to declare and use pipes in a DPC++ program

Sample 6: Improve Performance with Double Buffering  

This sample demonstrates how to parallelize host-side processing and buffer transfers between host and device with kernel execution and improve overall application performance.

CLI or IDE Sample Name Link to the Git Repository
double_buffering Double Buffering sample

Key concepts covered in this sample: 

  • The double buffering optimization technique
  • Determining when double buffering is beneficial
  • How to measure the impact of double buffering 

Next Steps

After going through the above samples, you can peruse the rest of the DPC++ FPGA samples (tutorials or reference designs) based on the dependency diagram. When going through the tutorials, do note that many of them build on concepts from other tutorials. You can also refer to the following resources:

Document Description
Get Started with Intel® oneAPI Base Toolkit on the DevCloud Refer to this guide for Intel DevCloud development sandbox-specific instructions.
Installation Guide for Intel® oneAPI Toolkits Learn about installing the Intel® oneAPI Base Toolkit and the Intel® FPGA Add-on for oneAPI Base Toolkit.
Intel® oneAPI Programming Guide Learn about oneAPI and DPC++, programming models, programming interfaces, DPC++ language and runtime, APIs, and software development processes.
Intel® oneAPI DPC++ FPGA Optimization Guide Learn how to optimize your design for the FPGA by leveraging the functionalities of DPC++ and the underlying hardware.
Get Started with the Intel® oneAPI Base Toolkit for Linux* Refer to this guide for Linux-specific getting started instructions.
Get Started with the Intel® oneAPI Base Toolkit for Windows* Refer to this guide for Windows-specific getting started instructions.
FPGA Tutorials  Refer to these tutorials for more in-depth instructions about how to use the tutorials.
DPC++ Foundations Code Sample Walk-Through Refer to this guide for a code walk-through for Data Parallel C++ (DPC++) foundations.
FPGA oneAPI Training Visit our training site for webinars and quick videos.
SYCL Specification (v 1.2.1) The SYCL Specification version 1.2.1 from Khronos.
Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems Using C++ and SYCL Third-party open access book on learning how to accelerate C++ programs using data parallelism. This book enables C++ programmers to be at the forefront of this exciting and important new development that is helping to push computing to new levels. It is full of practical advice, detailed explanations, and code examples o illustrate key topics.

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