IDF15 - Webcast: Code Modernization Best Practices

Published: 10/30/2015, Last Updated: 10/30/2015

Code Modernization Best Practices: Multi-level Parallelism for Intel® Xeon® and Intel® Xeon Phi™ Processors

Intel® Xeon® and Intel® Xeon Phi™ processor based platforms provide multiple levels of parallel execution resources. The amount of compute power of these resources is growing with every product generation, yet most applications do not fully utilize the available computing resources. This session will provide details on the growth in hardware resources and characterize performance using different levels of parallelism. Also covered are the key principles of how to use all levels of parallelism with clear examples and supporting data.

Topics include:

  • Parallel computing resources in Intel® Architecture (IA)
  • The parallel programming model for IA
  • Best practices in parallelizing serial code
  • The limitations of performance portability
  • Summary

Speaker: Robert Geva Principal Engineer, Manager of Financial Services Engineering Group, Intel Corporation

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Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804