Intel C++ Compiler 16.0 Update 4 for Linux* Release Notes for Intel Parallel Studio XE 2016

By Kenneth M Craft, Published: 07/06/2015, Last Updated: 09/14/2016

This document provides a summary of new and changed product features and includes notes about features and problems not described in the product documentation. 

Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 16.0 Update 4

Change History

Changes in Update 4 (Intel® C++ Compiler 16.0.4)

  • Fixes for reported problems
  • Documentation updates

Changes in Update 3 (Intel® C++ Compiler 16.0.3)

  • Added support for Intel® Xeon Phi™ processor (codename: Knights Landing)
  • Fixes for reported problems
  • Documentation updates

Changes in Update 2 (Intel® C++ Compiler 16.0.2)

Changes in Update 1 (Intel® C++ Compiler 16.0.1)

 

Changes since Intel® C++ Compiler 15.0 (New in Intel® C++ Compiler 16.0.0)

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System Requirements

  • A PC based on an IA-32 or Intel® 64 architecture processor supporting the Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instructions (Intel® Pentium® 4 processor or later, or compatible non-Intel processor)
    • Development of 64-bit applications or applications targeting Intel® MIC Architecture is supported on a 64-bit version of the OS only.  Development of 32-bit applications is supported on either 32-bit or 64-bit versions of the OS
    • Development for a 32-bit on a 64-bit host may require optional library components (ia32-libs, lib32gcc1, lib32stdc++6, libc6-dev-i386, gcc-multilib, g++-multilib) to be installed from your Linux distribution.
  • For Intel® MIC Architecture development/testing:
  • For offload to or native support for Intel® Graphics Technology development/testing
    • Offload is supported from 64-bit applications only
    • A 64-bit graphics driver with support for Intel® Graphics Technology (available from the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com). You should have access to the Intel® HD Graphics Drivers for Linux* download area as part of your Intel® Parallel Studio XE registration. If you do not see this area, please contact support. The following driver versions, and corresponding operating systems, are supported:
      • Intel® HD Graphics Drivers for Linux* version 16.3.2 for 3rd and 4th Generation Intel® Core™ Processors
        • SUSE LINUX Enterprise Server* 11 SP3
          • Kernel 3.14.5 (provides a pre-built i915 kernel module)
        • Ubuntu* 12.04 LTS
          • Kernel 3.2.0-41 for 3rd Generation Intel® Core™ Processors (provides a pre-built i915 kernel module)
          • Kernel 3.8.0-23 for 4th Generation Intel® Core™ Processors (provides a pre-built i915 kernel module)
      • Intel® HD Graphics Drivers for Linux* version 16.4.2 for 4th Generation Intel® Core™ Processors and 5th Generation Intel® Core™ Procesors
        • CentOS* 7.1 and RHEL 7.1
          • Kernel patches are provided for the default LTS kernel
    • The following processor models are supported: 
      • Intel® Xeon® Processor E3-1285 v3 and E3-1285L v3 (Intel® C226 Chipset) with Intel® HD Graphics P4700 
      • 4th Generation Intel® Core™ Processors with Intel® Iris™ Pro Graphics, Intel® Iris™ Graphics or Intel® HD Graphics 4200+ Series 
      • 3rd Generation Intel® Core™ Processors with Intel® HD Graphics 4000/2500 

        Please note: Intel® Xeon® processors are only supported with the chipsets listed. Intel® Xeon® configurations with other chipsets are not supported. Previous generations of Intel® Core™ processors are not supported. Intel® Celeron and Intel® Atom™ processors are also not compatible.
  • For the best experience, a multi-core or multi-processor system is recommended
  • 2GB of RAM (4GB recommended)
  • 7.5GB free disk space for all features
  • One of the following Linux distributions (this is the list of distributions tested by Intel; other distributions may or may not work and are not recommended - please refer to Technical Support if you have questions):
    • Fedora* 21, 22
    • Red Hat Enterprise Linux* 5, 6, 7
    • SUSE LINUX Enterprise Server* 11, 12
    • Ubuntu* 12.04 LTS (64-bit only), 13.10, 14.04 LTS, 15.04
    • Debian* 7.0, 8.0
    • Intel® Cluster Ready
  • Linux Developer tools component installed, including gcc, g++ and related tools
    • gcc versions 4.1-5.1 supported
    • binutils versions 2.17-2.25 supported
  • Library libunwind.so is required in order to use the –traceback option.  Some Linux distributions may require that it be obtained and installed separately.

Additional requirements to use the integration into the Eclipse* development environment

  • Eclipse Platform version 4.5 with:
    • Eclipse C/C++ Development Tools (CDT) 8.7 or later
    • Java* Runtime Environment (JRE) 7.0 (also called 1.7) or later
  • Eclipse Platform version 4.4 with:
    • Eclipse C/C++ Development Tools (CDT) 8.4 or later
    • Java* Runtime Environment (JRE) 7.0 (also called 1.7) or later
  • Eclipse Platform version 4.3 with:
    • Eclipse C/C++ Development Tools (CDT) 8.2 or later
    • Java* Runtime Environment (JRE) 6.0 (also called 1.6†) or later

† There is a known issue with JRE 6.0 through update 10 that causes a crash on Intel® 64 architecture.  It is recommended to use the latest update for your JRE.  See http://www.eclipse.org/eclipse/development/readme_eclipse_3.7.html section 3.1.3 for details.

Notes

  • The Intel compilers are tested with a number of different Linux distributions, with different versions of gcc. Some Linux distributions may contain header files different from those we have tested, which may cause problems. The version of glibc you use must be consistent with the version of gcc in use. For best results, use only the gcc versions as supplied with distributions listed above. 
  • The default for the Intel® compilers is to build IA-32 architecture applications that require a processor supporting the Intel® SSE2 instructions - for example, the Intel® Pentium® 4 processor. A compiler option is available to generate code that will run on any IA-32 architecture processor.
  • Compiling very large source files (several thousands of lines) using advanced optimizations such as -O3, -ipo and -openmp, may require substantially larger amounts of RAM.
  • The above lists of processor model names are not exhaustive - other processor models correctly supporting the same instruction set as those listed are expected to work. Please refer to Technical Support if you have questions regarding a specific processor model
  • Some optimization options have restrictions regarding the processor type on which the application is run. Please see the documentation of these options for more information.

Intel® Manycore Platform Software Stack (Intel® MPSS)

The Intel® Manycore Platform Software Stack (Intel® MPSS) may be installed before or after installing the Intel® C++ Compiler.
Using the latest version of Intel® MPSS available is recommended. It is available from the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com as part of your Intel® Parallel Studio XE for Linux* registration.
Refer to the Intel® MPSS documentation for the necessary steps to install the user space and kernel drivers. 

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How to use the Intel® C++ Compiler

The Getting Started Guide at <install-dir>/documentation_2016/ps2016/getstart_comp_lc.htm. contains information on how to use the Intel® C++ Compiler from the command line and from Linux*.

The Intel® C++ Compiler for Linux* does not provide "modulefiles" for usage with the Environmental Modules software utility, but is well suited for such usage.  See Using Environment Modules with Intel Development Tools for further information.

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Documentation

Product documentation is linked from <install-dir>/documentation_2016/en/ps2016/getstart_comp_lc.htm.  Full documentation for all tool components is available at the Intel® Parallel Studio XE Support page.

Intel-provided debug solutions

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Samples

Product samples can be located in the <install-dir>/samples_2016/en/compiler_c/psxe directory.

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Technical Support

If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.

For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/ 
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.

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New and Changed Features

The following features are new or significantly enhanced in this version.  For more information on these features, please refer to the documentation.

Intrinsics for the Short Vector Random Number Generator (SVRNG) Library

  • The Short Vector Random Number Generator (SVRNG) library provides intrinsics for the IA-32 and Intel® 64 architectures running on supported operating systems.  The SVRNG library partially covers both standard C++ and the random number generation functionality of the Intel® Math Kernel Library (Intel® MKL).  Complete documentation may be found in the Intel® C++ Compiler 16.0 User and Reference Guide.
  • Note: The SVRNG feature should not be used to target an Intel® Many Integrated Core Architecture (Intel® MIC Architecture) Intel® Advanced Vector Extensions 512 (Intel® AVX-512) CPU (second generation Intel® Xeon Phitm  processor code name Knights Landing).  Support is in Intel® C++ Compiler 16.0 Update 3 and later.

Support for new features in OpenMP* 4.5 Specification

 

  • Support for #pragma omp simd simdlen(n)
  • Support for #pragma omp ordered simd
  • Intel® processor clause extension added to #pragma omp declare simd (proposed; not officially part of OpenMP* 4.5)
  • The linear clause on the #pragma omp declare simd directive is extended with new modifiers:
    • linear (linear-list [ : linear-step]) where linear-list is one of:
      • list
      • modifier (list) where modifier is one of ref, val, or uval
    • All list items must be arguments of the function that will be invoked on each SIMD lane
    • If no modifier is specified, or if the val or uval modifier is specified, the value of each list item on each lane corresponds to the value of the list item upon entry to the function plus the logical number of lanes times linear-step
    • If the uval modifier is specified, each invocation uses the same storage location for each SIMD lane; this storage location is updated with the final value of the logically last lane
    • If the ref modifier is specified, the storage location of each list item on each lane corresponds to an array at the storage location upon entry to the function indexed by the logical number of the lane times linear-step

Intel® C++ Compiler SIMD Data Layout Templates (SDLT)

  • SDLT is a library that helps you leverage SIMD hardware and compilers without having to be a SIMD vectorization expert.
  • SDLT can be used with any compiler supporting ISO C++11, Intel® Cilktm Plus SIMD extensions, and #pragma ivdep
  • Intel® C++ Compiler SIMD Data Layout Templates:
    • Enable you to program in an AOS style while data layout is SOA for vectorization
    • Target effective SIMD vectorization for performance
    • Are compatible with other explicit SIMD programming models
  • For SDLT to generate efficient SIMD code, the following compiler options are required or recommended:
    • C++11 support
      • /Qstd:c11 (Windows*) or -std=c11 (Linux*)
    • Code optimization level of 2 or higher
      • /O2 or /O3 (Windows*) or -O2 or -O3 (Linux*)
    • ANSI aliasing rules in optimizations
      • /Qansi-alias (Windows*) or -ansi-alias (Linux*)
    • Optionally tell the compiler which processor features it may target
      • /Qxcode (Windows*) or -xcode (Linux*)
    • Optionally tell the compiler to generate multiple, feature-specific auto-dispatch code paths for Intel® processors if there is a performance benefit
  • GCC 4.7 or later is required for SDLT to work on Linux* due to C++11 dependencies.  GCC 4.8 or later is recommended for using Intel® SDLT with STL algorithms.
  • Microsoft Visual Studio* 2012 or later is required for SDLT to work on Windows* due to C++11 dependencies

Support for additional OpenMP* 4.0 features

  • Support for #pragma omp declare reduction to define user-defined reductions
  • Support for #pragma omp simd collapse(n)

Intel® Data Analytics Acceleration Library (Intel® DAAL)

  • Intel® DAAL boosts big data analytics and machine learning performance with this easy-to-use library.

C++14 features supported
The Intel® C++ Compiler 16.0 supports the following features with compiler option /Qstd:c++14 (Windows*) or -std=c++14 (Linux*/OS X*)

C11 features supported

The Intel® C++ Compiler 16.0 supports the following features with compiler option /Qstd:c11 (Windows*) or -std=c11 (Linux*/OS X*)

-fstack-protector-strong now supported
The Intel(R) C++ Compiler now supports the gcc* 4.9 option -fstack-protector-strong.

Intel(R) Math Kernel Library (Intel(R) MKL) with Intel(R) Threading Building Blocks (Intel(R) TBB) Threading Layer supported
The Intel(R) C++ Compiler adds support for using the Intel MKL threading layer support for Intel TBB. These libraries will be used when both /Qmkl and /Qtbb (Windows*) or -mkl and -tbb (Linux* / OS X*) are specified and /Qopenmp, -qopenmp, or -fopenmp are not specified. If OpenMP* is required, but you want to utilize the Intel MKL libraries that use Intel TBB, you will need to explicitly specify the libraries at link time.

API to query Intel(R) Graphics Technology capabilities at runtime added
The APIS _GFX_get_device_platform(void), _GFX_get_device_sku(void), _GFX_get_device_hardware_thread_count(void), _GFX_get_device_min_frequency(void), _GFX_get_device_mas_frequency(void), and _GFX_get_device_current_frequency(void) have been added to provide a source-level method of obtaining hardware information about the Intel Graphics Technology at runtime. 

API to set thread space configuration at runtime added 
The API _GFX_set_thread_space_config(int, int, int, int) has been added to allow the application to programmatically control the thread space and thread group height and width at runtime.
The runtime environment variables GFX_THREAD_SPACE_WIDTH and GFX_THREAD_SPACE_HEIGHT have been added to allow the application to programmatically control the thread space width and height at runtime. These are in addition to the GFX_THREAD_GROUP_WIDTH and GFX_THREAD_GROUP_HEIGHT environment variables for controlling the thread group width and height.

New targetptr and preallocated offload modifiers for Intel® Many Integrated Core Architecture (Intel® MIC Architecture)

The offload syntax will be extended with two new modifiers: targetptr and preallocated. Use of these modifiers permits allocating Intel® MIC Architecture-only memory through #pragma offload (targetptr) or by the user in his offload code (preallocated targetptr).

New offload streams support to offload multiple concurrent computations to Intel® Many Integrated Core Architecture (Intel® MIC Architecture) from a single CPU thread

New APIs (_Offload_stream_handle, _Offload_stream_completed, _Offload_device_streams_completed) and additional offload pragma clauses (stream, signal) are now available to implement offloading multiple computations to Intel® MIC Architecture to be executed in parallel on the target device.  See the Intel® C++ Compiler 16.0 User’s Guide for further details on the offload streams API.

To use offload streams, it is necessary to set the following environment variables as follows:

  • MIC_ENV_PREFIX=MIC
  • MIC_KMP_AFFINITY=norespect,none
  • OFFLOAD_STREAM_AFFINITY={compact | scatter}

regparm calling convention ABI change

The regparm calling convention is now aligned with the ABI as implemented in gcc* 4.0. This breaks compatibility with previous Intel® C++ Compiler versions. To revert to the previous behavior, use -mregparm-version=1.

Basic arithmetic and logical operators now supported for integer vector types

Variables of int datatypes that use the vector_size attribute can now take advantage of basic operators as described in the gcc documentation* at http://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html.

Linux* split DWARF debug info (also known as DWARF fission) now supported

The Intel® C++ Compiler 16.0 has added the -gsplit-dwarf compiler option which will generate an additional object file with the .dwo extension which will contain the majority of debug information. Currently this is only supported for 32-bit and 64-bit targets. Compiling with this option will require binutils 2.23 or later and debugging will require gdb* 7.5 or later.

gfx_sys_check utility to validate support for offloading to Intel® Graphics Technology

A utility, gfx_sys_check, is now provided to confirm a platform’s support for offloading to Intel® Graphics Technology. The utility also provides extra details relevant to Intel Graphics Technology.

Shared local memory support for Intel® Graphics Technology

A new _Thread_group clause for cilk_for loops, a new __thread_group_local type and storage qualifier, and a new API _gfx_gpgpu_thread_barrier() are now provided to enable sharing local memory between threads on Intel® Graphics Technology to reduce RAM traffic and improve performance.

cilk_for loops now accepted with #pragma simd
C/C++ for loops parallelized using the Intel® Cilk™ Plus cilk_for keyword can now also be targeted for explicit vectorization using either #pragma simd or the _Simd keyword.

Enable respect for parentheses when determining order of operations in expressions
The /Qprotect-parens (Windows*) and -fprotect-parens (Linux*/OS X*) require the compiler optimizer to honor parentheses when evaluation expressions and to not reassociate operations. For example, when these options are used, the compiler would no longer be free to convert:

double y = (a + b) + c;

to

double y = a + (b + c);

These options are not enabled by default, and their use may negatively impact performance.

Compiler intrinsic functions now defined internally
To improve compilation time, the Intel® C++ Compiler 16.0 no longer checks header files for intrinsic function declarations. This can impact type-checking, so to add the function prototypes for this purpose, add the compiler option -D__INTEL_COMPILER_USE_INTRINSIC_PROTOTYPES.

BLOCK_LOOP and NOBLOCK_LOOP pragmas and private clause for unroll_and_jam pragma added
New and updated pragmas have been added to provide loop blocking information to the compiler. This includes new pragmas #pragma BLOCK_LOOP [clause[[,] clause...] ] and #pragma NOBLOCK_LOOP. This also includes the addition of a private(var list) clause to the #pragma unroll_and_jam. See the Intel® C++ Compiler User’s Guide for details.

New and Changed Compiler Options
For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 16.0 User's Guide.

  • -daal[= lib]     Tells the compiler to link certain libraries in the Intel® Data Acceleration Library (Intel® DAAL)
  • -mgpu-asm-dump[=filename]  Tells the compiler to generate a native assembly listing for the processor graphics code to be offloaded.  This option only applies to Intel® Graphics Technology
  • -mregparm-version=n   Determines which version of the Application Binary Interface (ABI) is used for the regparm parameter passing convention
  • -print-sysroot   Prints the target sysroot directory that is used during compilation
  • -qoffload-arch=arch  [: visa]  Lets you specify the target architecture to use when offloading code.  This option only applies to Intel® MIC architecture and Intel® Graphics Technology.  For Intel® Graphics Technology, you can also specify a virtual ISA (vISA)
  • -qoffload-svm   Determines whether the compiler uses Shared Virtual Memory (SVM) mode.  This option only applies to Intel® Graphics Technology
  • -qopt-prefetch-issue-excl-hint  Supports the prefetchW instruction in Intel® microarchitecture code name Broadwell and later

For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler 16.0 User's Guide.

Compiler options starting with –o are deprecated
All compiler options starting with –o are deprecated. These will be replaced by new options preceded with –q. For example, -opt-report should now be –qopt-report. This is to improve compatibility with third-party tools that expect –o<text> to always refer to output filenames.

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Support Deprecated

Red Hat Enterprise Linux 5* is deprecated

Support for Red Hat Enterprise Linux 5* is deprecated and will be removed in a future release.

Installation on 32-bit hosts is deprecated

Installation on 32-bit hosts is deprecated and will be removed in a future release. However, support for generating code for 32-bit targets will still be supported.

Intel® HD Graphics Drivers for Linux* version 16.3.2 for 3rd and 4th Generation Intel® Core™ Processors are deprecated

Support for the 16.3.2 driver is deprecated and will be removed in a future release.  Intel recommends migrating to the 16.4.2 driver and its supporting operating system (either CentOS* 7.1 or RHEL 7.1) for systems based on 4th Generation Intel® Core™ Processors.

 Operating systems supporting Intel® HD Graphics Drivers for Linux* version 16.3.2 are deprecated

Support for SLES 11 SP3 and Ubuntu 12.04 LTS is deprecated and will be removed in a future release.

GFX offload support for 3rd Generation Intel® Core™ Processors is deprecated

GFX offload support to processor graphics for 3rd Generation Intel® Core™ Processors is deprecated and will be removed in Intel® C++ Compiler 17.0

_GFX_enqueue  is deprecated

_GFX_enqueue is deprecated and should be replaced with _GFX_offload 

Support Removed

Debian 6* is Not Supported

Support has been removed for installation and use on these operating system versions. Intel recommends migrating to a newer version of these operating systems.

Fedora 20* is Not Supported

Support has been removed for installation and use on these operating system versions. Intel recommends migrating to a newer version of these operating systems.

Eclipse 3.8 is Not Supported

Support has been removed for installation and use on these IDEs. Intel recommends migrating to a newer version of these IDEs.

Static Analysis Not Supported
Support for Static Analysis is no longer supported. If you have concerns or feedback, please comment.

Mudflap library Not Supported
-fmudflap and the Mudflap library are no longer supported.

 

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Known Limitations

Pointer Checker requires a dynamic runtime library

When using the -check-pointers option, the runtime library libchkp.so must be linked in. When using options like -static or -static-intel with -check-pointers, be aware that this dynamic library will be linked in regardless of your settings. See the article at http://intel.ly/1jV0eWD for more information.

Known Issues with Intel® Many Integrated Core Architecture (Intel® MIC Architecture)

  • Set MIC_LD_LIBRARY_PATH before loading shared libraries containing offloaded code

    When loading a shared object within your program with dlopen, the setting of the MIC_LD_LIBRARY_PATH variable is required in order to pick up the *.so if the .so contains offload.  This is true even if the .so is brought in with a relative or full path (i.e. dlopen("../../libmylib.so", <flag>))

  • Using offload code in shared libraries requires main program to be linked with -qoffload=mandatory or -qoffload=optional option

    There is initialization required for offload that can only be done in the main program. For offload code in shared libraries, this means that the main program must also be linked for offload so that the initialization happens. This will happen automatically if the main code or code statically linked with the main program contains offload constructs. If that is not the case, you will need to link the main program with the -qoffload=mandatory or -qoffload=optional compiler options.
     
  • Missing symbols not detected at link time for the offload compilation model

    -offload-option,mic,compiler,"-z defs" is no longer needed to detect missing symbols at link time.
     
  • *MIC* tag added to compile-time diagnostics

    The compiler diagnostics infrastructure is modified to add an additional offload *MIC* tag to the output message to allow differentiation from the target (Intel® MIC Architecture) and the host CPU compilations. The additional tag appears only in the target compilation diagnostics issued when compiling with offload extensions for Intel® MIC Architecture.

    In the examples below the sample source programs trigger identical diagnostics during both the host CPU and Target Intel® MIC Architecture compilations; however, some programs will generate different diagnostics during these two compilations. The new tag permits easier association with either the CPU or Target compilation

    $ icc -c sample.c

    sample.c(1): warning #1079: *MIC* return type of function "main" must be "int"
    void main()
           ^
    sample.c(5): warning #120: *MIC* return value type does not match the function type
      return 0;
                 ^
    sample.c(1): warning #1079: return type of function "main" must be "int"
     void main()
            ^
    sample.c(5): warning #120: return value type does not match the function type
      return 0;

     
  • Runtime Type Information (RTTI) not supported

    Runtime Type Information (RTTI) is not supported under the Virtual-Shared memory programming method; specifically, use of dynamic_cast<> and typeid() is not supported.
     
  • Direct (native) mode requires transferring runtime libraries like libiomp5.so to coprocessor

    The Intel® Manycore Platform Software Stack (Intel® MPSS) no longer includes Intel compiler libraries under /lib, for example the OpenMP* library, libiomp5.so.

    When running OpenMP* applications in direct mode (i.e. on the coprocessor card), users must first upload (via scp) a copy of the Intel® MIC Architecture OpenMP* library (<install_dir>/compilers_and_libraries_2016/linux/lib/mic/libiomp5.so) to the card (device names will be of the format micN, where the first card will be named mic0, the second mic1, and so on) before running their application.

    Failure to make this library available will result in a run-time failure like:

    /libexec/ld-elf.so.1: Shared object "libiomp5.so" not found, required by "sample"

    This can also apply to other compiler runtimes like libimf.so. The required libraries will depend on the application and how it’s built.
     
  • Calling exit() from an offload region

    When calling exit() from within an offload region, the application terminates with an error diagnostic “offload error: process on the device 0 unexpectedly exited with code 0

Known issues for offload to Intel® Graphics Technology

  • Host-side execution of offload code is not parallelized

    The compiler will generate both a target and host version of the parallel loop under #pragma offload. The host version is executed when the offload cannot be performed (usually when the target system does not have a unit with Intel® Graphics Technology enabled).The parallel loop must be specified using the parallel syntax of cilk_for or an Array Notation statement, which has parallel semantics for offload. The target version of the loop will be parallelized for target execution, but there is a current limitation where the host-side back-up version of the parallel loop will not be parallelized. Please be aware this can affect the performance of the back-up code execution significantly when offload execution does not happen in the case of cilk_for use. Array notation does not currently generate parallel code on the host, so performance should not differ here in that case. This is a known issue that may be resolved in a future product release.
     
  • If multiple processes running with non-root privilege try to offload there may be sporadic fails.

    You may see sporadic fails if multiple processes (with non-root privilege) try to offload. Only the first process that opens /dev/dri/card0 can pass DRM authentication. Only the first process to open /dev/dri/card0 has master privilege.  “Root” or “master” privilege is needed to pass the DRM authentication. That is why all processes pass through when running with root privilege, but only one of them passes with non-root privilege. This is a known restriction for Linux*.

    Possible workarounds
    • Execute each process serially.
    • Execute as root
  • Other known limitations with offload to Intel® Graphics Technology
    • In the offloaded code, the following are not allowed:
      • Exception handling
      • RTTI
      • longjmp/setjmp
      • VLA
      • Variable parameter lists
      • Virtual functions, function pointers, or other indirect calls or jumps
      • Shared virtual memory
      • Data structures containing pointers, such as arrays or structs
      • Globals with pointer or reference type
      • OpenMP*
      • cilk_spawn or cilk_sync
      • Intel® Cilk™ Plus reducers
      • ANSI C runtime library calls (with the exception of SVML, math.h, and mathimf.h calls and a few others)
    • 64-bit float and integer operations are inefficient

Intel® Cilk™ Plus Known Issues

  • Static linkage of the runtime is not supported 

    Static versions of the Intel® Cilk™ Plus library are not provided by design.  Using -static-intel to link static libraries will generate an expected warning that the dynamic version of the of Intel® Cilk™ Plus library, libcilkrts.so, is linked.

    $ icc -static-intel sample.c

    icc: warning #10237: -lcilkrts linked in dynamically, static library not available


    Alternatively, you can build the open source version of Intel Cilk Plus with a static runtime.  See http://cilk.com for information on this implementation of Intel Cilk Plus. Any issues must be reported using the dynamic version of the Intel® Cilk™ Plus library.

Guided Auto-Parallel Known Issues

  • Guided Auto Parallel (GAP) analysis for single file, function name or specific range of source code does not work when Whole Program Interprocedural Optimization (-ipo) is enabled

SPEC CPUv6 runtime bus error seen on Red Hat Enterprise Linux* 6 with the Intel® IA-32 C++ compiler

  • If the SPEC CPUv6 benchmark (currently in development) is compiled with the Intel® IA-32 C++ compiler and then run with restricted stack and/or virtual memory limits using the ulimit command e.g., ulimit -s 2067152 -v 15000000, bus errors may be seen.  Although this has only been observed on this benchmark, it may apply to other applications.  A known workaround is to set these parameters to unlimited.

GCC 6.0 is not supported

  • GCC 6.0 is currently in development and is not supported for use with  Intel® C++ Compiler 16.0 Update 2.  If the compiler is used with GCC 6.0 to compile C++ files, the following informational error will be provided: "Error #3802: Version 16.0 Update 2 is incompatible with GNU versions greater than or equal to 6.0, due to an incomplete implementation of SFINAE which is used extensively in gcc6 headers. If you wish to proceed, use option -wd3802"

Spurious error when a call to a template dependent function is made in a decltype expression in an out-of-line definition for a late-specified return type

  • This is a known regression in Intel® C++ Compiler 16.0 Update 2.  An example is:
  • template <class T>
    struct C {
      int then(int*,int*);
      template <class T2>
      auto then(T2 arg) -> decltype(this->then(&arg, &arg));
    };
    template <class T>
    template <class T2>
    auto C<T>::then(T2 arg) -> decltype(this->then(&arg, &arg)) { return 0; }
    void foo() {
       C<int> f;
       f.then(99);
    }
    

    To work around this problem, the definition can be moved inline, or the use of a late-specified return type should be avoided (by explicitly declaring the return type). 

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For more complete information about compiler optimizations, see our Optimization Notice.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804