Intel® C++ Compiler 19.0 for Windows* Host Release Notes for Intel® System Studio 2019

By Devorah Hayman,

Published:05/30/2018   Last Updated:12/20/2018

This document provides a summary of new and changed features of the Intel® C++ Compiler for applications running on Embedded Linux* and Android* targets.  It also includes notes about features and problems not described in the product documentation.

Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 19.0.

Change History

Changes since Intel® C++ Compiler 19.0.4 (New in Intel® C++ Compiler 19.0.5)

  • Corrections to reported problems
  • Includes certain functional and security updates.  We recommend updating for these functional and security updates.
  • The Intel® C++ Compiler in this update includes a new /Qnextgen compiler option that uses LLVM Technology.  See the special Additional Requirements for ICC NextGen and the ICC NextGen Notes below for more details.

Changes since Intel® C++ Compiler 19.0.3 (New in Intel® C++ Compiler 19.0.4)

  • Corrections to reported problems

Changes since Intel® C++ Compiler 19.0.2 (New in Intel® C++ Compiler 19.0.3)

  • Corrections to reported problems

Changes since Intel® C++ Compiler 19.0.1 (New in Intel® C++ Compiler 19.0.2)

  • Intel® C++ Compiler 19.0 Update 2 includes functional and security updates. Users should update to the latest version.

Changes since Intel® C++ Compiler 19.0 (New in Intel® C++ Compiler 19.0 Update 1)

Changes since Intel® C++ Compiler 18.0 (New in Intel® C++ Compiler 19.0)

System Requirements

For an explanation of architecture names, see http://intel.ly/q9JVjE 

 Host Hardware Requirements

  • A PC based on an Intel® 64 architecture processor supporting the Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instructions (Intel® 2nd Generation or newer Generation of Intel® Core™ i3, i5, or i7 processors and Intel® Xeon® E3 or E5 Processor family, or compatible non-Intel processor)
  • Development of 64-bit applications or applications targeting Intel® MIC Architecture is supported on a 64-bit version of the OS only.  Development of 32-bit applications is now supported on a 64-bit version of the OS only.  The compiler cannot be installed on a 32-bit OS.
  • Development for a 32-bit target on a 64-bit host may require optional library components (ia32-libs, lib32gcc1, lib32stdc++6, libc6-dev-i386, gcc-multilib, g++-multilib) to be installed from your Linux distribution.
  • For the best experience, a multi-core or multi-processor system is recommended
  • 2GB of RAM (4GB recommended)
  • 4GB free disk space for all features

 Host Software Requirements

  • Microsoft Windows 7* (SP1), Microsoft Windows 8*, Microsoft Windows 8.1* or Windows 10*
  • The prerequisite for successful Wind River* Linux* targeted cross-build environment integration is
    • Wind River* Workbench for Wind River* Linux* 7.x - 8.x
  • The prerequisite for successful Android* targeted cross-build environment integration is
    • Android* NDK version r16, r17
    • Android* Open Source Project (AOSP) workspace, for example, AOSP workspace for Android 7.0 or Android 8.0

Additional Requirements to use the /Qnextgen Option

For the /Qnextgen option to use LLVM Technology only the following are supported:

  • For Intel64, supported Windows OSes and Visual Studio - only those listed below:
    • Windows 10
    • Windows Server 2019
    • Windows Server 2016 (1607)
    • Visual Studio 2019 with Windows SDK 10
    • Visual Studio 2019 Build Tools* with Windows SDK 10 
    • Visual Studio 2017 with Windows SDK 10

NOTES

  • The default for the Intel® compilers is to build IA-32 architecture applications that require a processor supporting the Intel® SSE2 instructions - for example, the Intel® Pentium® 4 processor. A compiler option is available to generate code that will run on any IA-32 architecture processor.  However, if your application uses Intel® Integrated Performance Primitives or Intel® Threading Building Blocks, executing the application will require a processor supporting the Intel® SSE2 instructions.
  • Compiling very large source files (several thousands of lines) using advanced optimizations such as -O3 or -ipo may require substantially larger amounts of RAM.
  • The above lists of processor model names are not exhaustive - other processor models correctly supporting the same instruction set as those listed are expected to work. Please refer to Technical Support if you have questions regarding a specific processor model.
  • Some optimization options have restrictions regarding the processor type on which the application is run. Please see the documentation of these options for more information.

Target Hardware Requirements

  • Development platform based on the Intel Atom® processor Z5xx, N4xx, N5xx, D5xx E6xx, N2xxx, D2xxx, Z2xxx, Z3xxx, E3xxx, S1xxx, C2xxx, C3xxx, Intel Atom® processor X Series, the Intel Atom® processor CE4xxx, CE53xx or the Intel® Puma6™ Media Gateway.

  • Alternatively development platform based on 4th, 5th, 6th,7th or 8th generation Intel® Core™ microarchitecture based Intel® Core™ processor or Intel® Xeon® Processor

  • Development targeting Intel® Quark™ processor X1xxx, D1xxx, D2xxx,  Intel® Quark™ SE C1xxx

  • Needed hard disk space

    • 13MB(IA-32)/15MB(intel64)

Target Software Requirements

The target platform should be based on one of the following environments:

  • Yocto Project* 1.7, 1.8, 1.9, 2.0, 2.2, 2.3  based environment
  • Wind River* Linux*  7, 8, 9  based environment 
  • openSUSE* 13.2
  • Tizen* IVI 2.0, 3.0 
  • Android* Nougat

How to use the Intel® C++ Compiler

Intel System Studio 2019: Getting Started with the Intel® C++ Compiler 19.0* at <install-dir>\documentation_2019\en\compiler_c\iss2019\l_a_compiler_get_started.htm contains information on how to use the Intel® C++ Compiler from the command line and from Eclipse*.

The Intel® C++ Compiler for Linux* does not provide "modulefiles" for usage with the Environmental Modules software utility but is well suited for such usage.  See Using Environment Modules with Intel Development Tools for further information.

Documentation

Product documentation is linked from <install-dir>\documentation_2019\en\compiler_c\.  Full documentation for all tool components is available at the Intel System Studio Documentation page.

Offline Core Documentation Removed from the Installed Image

The core documentation for the components of Intel® System Studio is available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration CenterProduct List > Intel® System Studio Documentation.

Intel-provided debug solutions

Samples

Product samples are now available online at Intel® Software Product Samples and Tutorials.

Technical Support

If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates, and upgrades for the duration of the support term.

For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/ 
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.

New and Changed Features

The following features are new or significantly enhanced in this version.  For more information on these features, please refer to the documentation.

Using the /Qnextgen Compiler Option

In Update 5 we allow a new compiler option, /Qnextgen.   This compiler option is provided as a way to use our LLVM Technology.    As an example, here are some suggested compiler options to exercise the LLVM Technology mode:

icl /Qnextgen -flto -Ofast

Note that /Qnextgen allows the LLVM* mode, then -flto -Ofast are Clang* options that are recognized in this new mode.  With /Qnextgen you can use either ICL options, Clang*/LLVM* options, or a mix of both. 

Value safe simd options for #pragma omp simd

Currently "#pragma omp simd" overrides FP value and exception safe settings. The following options change that legacy behaviour and produce value and exception safe code even for SIMD loops.

  • Qsimd-honor-fp-model[-]: Tells the compiler to obey the selected floating-point model when vectorizing SIMD loops
  • Qsimd-serialize-fp-reduction[-]: Tells the compiler to serialize floating-point reduction when vectorizing SIMD loops.

OpenMP SIMD specification and FP model flag can contradict in the requirement. Compiler’s default is to follow OpenMP specification and vectorize the loop. With this new flag, a programmer can override so that the compiler follows the FP model flag instead and serialize the loop.
Note 1: When –qsimd-honor-fp-model is used and OpenMP SIMD reduction specification is the only thing causing serialization of entire loop addition of qsimd-serialize-fp-reduction will result in vectorization of the entire loop except reduction calculation which will be serialized.
Note 2: This option does not affect auto-vectorization of loops.

New code names are to be supported in -[Q]x / -[Q]ax / -[m]tune / -[m]arch options.

Code names supported :cascadelake, kabylake, coffeelake, amberlake, whiskeylake.

nodynamic_align and vectorlength clauses for pragma vector

  • Explicit syntax for dynamic alignment
    #pragma vector dynamic_align[(pointer)] #pragma vector nodynamic_align

    With no pointer specified, compiler behaves normally (automatically decides which pointer has to be aligned or doesn’t generate peel loop at all). With pointer specified, compiler generates peel loop for that pointer. With nodynamic_align clause, the compiler will not generate a peel loop.

  • #pragma vector vectorlength(vl1,vl2, .. , vln)
    #pragma vector vectorlength(vl1,vl2, .. , vln)

    Vectorizer chooses best vector length from the list according to cost model. If all vector length from the list are not profitable, the loop remains scalar. This pragma doesn’t force vectorization, thus it can be safely used for all loops.

Parallel STL for parallel and vector execution of the C++ STL
Features from OpenMP* TR4 Version 5.0 Preview 2

Language features from the OpenMP* Technical Report 6 : Version 5.0 Preview 2 specifications are now supported.

  • Explicit syntax for inclusive scan *
    #pragma omp simd[parallel] scan(scan-op: item-list)
    #pragma omp inclusive_scan(item-list)
  • Explicit syntax for exclusive scan *
    #pragma omp simd[parallel] scan(scan-op: item-list)
    #pragma omp inclusive_scan(item-list) 

    Prefix sum is computed correctly during vector execution
    *The syntax will be renamed in product release
     
  • UDI for OpenMP* Parallel pragmas
    #pragma omp declare induction ( induction-id : induction-type :step-type : inductor ) [collector( collector )]

For more information, see the compiler documentation or the link to the OpenMP* Specification above.

C++17 features supported

The Intel® C++ Compiler 19.0 beta supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/OS X*) options:

  • Fold expressions(N4295)
  • Inline variables(P0386R2)
  • Construction rules for enum classes(P0138R2)
  • Removing deprecated dynamic exception specifications(P0003R5)
  • Make exception specifications part of the type system(P0012R1)
  • constexpr lambda expressions(P0170R1)
  • Lambda capture of *this(P0018R3)
  • constexpr if-statements(P0292R2)
  • Structured bindings(P0217R3)
  • Separate variable and condition for if and switch(P0305R1)
  • Please see C++17 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

C++14 features supported

The Intel® C++ Compiler 19.0 beta supports the following features under the /Qstd=c++14 (Windows*) or -std=c++14 (Linux*/OS X*) options:

C++11 features supported

The Intel® C++ Compiler 19.0 beta supports the following features under the /Qstd=c++11 (Windows*) or -std=c++11 (Linux*/OS X*) options:

C11 features supported

The Intel® C++ Compiler supports the C11 features under the /Qstd=c11 (Windows*) or -std=c11(Linux*/OS X*) options:

New and Changed Compiler Options

For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 19.0 User's Guide.

  • -qopenmp-simd set by default
  • New -xcannonlake option
  • New -mtune=cannonlake option
  • -rcd option enabled “fast” float-to-integer conversions, by using round-to-nearest instead of truncating rounding. This option has been deprecated.

For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler 19.0 User's Guide.

Parallel STL for parallel and vector execution of the C++ STL

Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.

Features/APi changes

  • More algorithms support parallel and vector execution policies: find_first_of, is_heap, is_heap_until, replace, replace_if.
  • More algorithms support vector execution policies: remove, remove_if.
  • More algorithms support parallel execution policies: partial_sort.

To learn more, please refer to article https://software.intel.com/en-us/get-started-with-pstl

 

Support Deprecated

  • We have deprecated Intel® C++ Compiler support for the latest Android NDK r19 in this release. We will be removing Android* support in Intel® C++ Compiler starting in Intel® System Studio releases in the second half of 2019. If you have any questions, please see https://software.intel.com/en-us/support.

Support Removed

  • Support for installation on IA-32 hosts has been removed
    • Support for installation on IA-32 hosts has been removed.  Support for generating code for 32-bit targets is supported on 64-bit hosts (only) via compiler option /Qm32
  • Offload support for Intel® Graphics Technology has been removed
  • Intel® Cilk™ Plus feature is removed in the Intel® C++ Compiler 19.0. For more information see Migrate Your Application to use OpenMP* instead of Intel® Cilk™ Plus.

Known Limitations 

Parallel STL

unseq and par_unseq policies only have effect with compilers that support '#pragma omp simd' or '#pragma simd. Parallel and vector execution is only supported for a subset of algorithms if random access iterators are provided, while for the rest execution will remain serial. Depending on a compiler, zip_iterator may not work with unseq and par_unseq policies.

Pointer Checker requires a dynamic runtime library

When using the -check-pointers option, the runtime library libchkp.so must be linked in. When using options like -static or -static-intel with -check-pointers, be aware that this dynamic library will be linked in regardless of your settings. See the article at Pointer Checker in ICC for more information.

Disclaimer and Legal Information

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to:  http://www.intel.com/design/literature.htm 

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to: 

http://www.intel.com/products/processor%5Fnumber/

The Intel® C++ Compiler is provided under Intel’s End User License Agreement (EULA). 

Please consult the licenses included in the distribution for details.

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* Other names and brands may be claimed as the property of others.

Copyright © 2018 Intel Corporation. All Rights Reserved.

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Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804