Intel® C++ Compiler for macOS* 19.1 Release Notes for Parallel Studio XE 2020 Composer Edition for macOS*

By Varsha Madananth,

Published:04/04/2019   Last Updated:03/30/2020

Intel® C++ Compiler for macOS* 19.1 Release Notes for Parallel Studio XE 2020

This document provides a summary of new and changed product features and includes notes about features and problems not described in the product documentation. 

Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 19.1

Change History

This section highlights important from the previous product version and changes in product updates.  

 

Changes since Intel® C++ Compiler 19.1.1 (New in Intel® C++ Compiler 19.1.2)

  • Corrections to reported problems

Changes since Intel® C++ Compiler 19.1 (New in Intel® C++ Compiler 19.1.1)

  • Corrections to reported problems.
  • Support for Xcode* 11.3

Changes since Intel® C++ Compiler 19.0 (New in Intel® C++ Compiler 19.1)

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System Requirements

  • A 64-bit Intel®-based Apple* Mac* system host 
  • 2GB RAM minimum, 4GB RAM recommended
  • 14GB free disk space
  • One of the following combinations of mac OS*, Xcode* and the Xcode SDK: 
    • macOS* 10.15 and Xcode* 11.x
    • macOS* 10.14 and Xcode*10.x
  • If doing command line development, the Command Line Tools component of Xcode* is required

Note: Advanced optimization options or very large programs may require additional resources such as memory or disk space.

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How to use the Intel® C++ Compiler

Parallel Studio XE 2020 : Getting Started with the Intel® C++  Compiler 19.1 for mac OS* at <install_dir>/documentation_2020/en/compiler_c/ps2020/get_started_mc.htm contains information on how to use the Intel® C++ Compiler from the command line and from Xcode*.

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Documentation

Product documentation is linked from <install-dir>/documentation_2020/en/compiler_c/ps2020/get_started_mc.htm.  Full documentation for all tool components is available at the Intel® Parallel Studio XE Support page.

Offline Core Documentation Removed from the Installed Image

Offline core documentation is removed from the Intel® Parallel Studio XE installed image. The core documentation for the components of Intel® Parallel Studio XE are available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® Parallel Studio XE Documentation.

Please use the instructions from this article to add Intel® Compiler documentation to your local machine.

Intel-provided debug solutions

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Samples

Product samples are now available online at Intel® Software Product Samples and Tutorials

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Redistributable Libraries

Refer to the Redistributable Libraries for Intel® Parallel Studio XE for more information.

Technical Support

If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.

For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/ 
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.

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New and Changed Features

Features from OpenMP 5.0*

  • IF clause on SIMD directive
  • NONTEMPORAL clause on SIMD directive

C++20 features supported

The Intel® C++ Compiler 19.1 supports the following features under the /Qstd=c++20 (Windows*) or -std=c++20 (Linux*/OS X*) options:

  • std::is_constant_evaluated and __builtin_is_constant_evaluated

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Parallel STL for parallel and vector execution of the C++ STL

Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.

Features/API changes

  • More algorithms support parallel and vector execution policies: find_first_of, is_heap, is_heap_until, replace, replace_if.
  • More algorithms support vector execution policies: remove, remove_if.
  • More algorithms support parallel execution policies: partial_sort.

To learn more, please refer to article https://software.intel.com/en-us/get-started-with-pstl

Support Deprecated

The Loop Profiler feature will be removed in future compilers.

The following compiler options related to Loop Profiler are deprecated and will be removed in future compilers

  • profile-loops=keyword
  • profile-loops-report=value
  • profile-functions
  • guide-profile

 

Support Removed

Intel® Cilk™ Plus support is removed in 19.1

This includes the "#pragma simd" directive.  Users should replace with the OpenMP SIMD pragma "#pragma omp simd" and it's clauses.  Remember to add compiler option "-qopenmp-simd" or "-qopenmp".  This pragma will be removed in future releases.

 

Known Limitations

Tachyon removed from samples

Xcode* 10 and Xcode* 11, new build system not supported

The Xcode 10 Beta introduced a “New Build System (Default)” which currently do not support custom compilers.You will see the error "no rule to process file" when building an Intel C++ Compiler project within XCode 10 and Xcode 11.  To use Intel compilers, switch to “Legacy Build System” in Project Settings.

Parallel STL

unseq and par_unseq policies only have effect with compilers that support '#pragma omp simd' or '#pragma simd. Parallel and vector execution is only supported for a subset of algorithms if random access iterators are provided, while for the rest execution will remain serial. Depending on a compiler, zip_iterator may not work with unseq and par_unseq policies.

 

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Disclaimer and Legal Information

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to:  http://www.intel.com/design/literature.htm 

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to: 

http://www.intel.com/products/processor%5Fnumber/

The Intel® C++ Compiler is provided under Intel's End User License Agreement (EULA). 

Please consult the licenses included in the distribution for details.

Intel, Intel logo, and Cilk are trademarks of Intel Corporation in the U.S. and other countries.

* Other names and brands may be claimed as the property of others.

Copyright © 2020 Intel Corporation. All Rights Reserved.

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Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804