Professor Mark Parsons
Mr Adrian Jackson
Dr Michèle Weiland
The Intel® Parallel Computing Centre at EPCC, the supercomputing centre at The University of Edinburgh, will build on the organisation’s extensive collaborations with academic and industrial partners, and its access to a wide range of hardware resources, to enable the optimisation of a set of widely used simulation codes on Intel® Xeon hardware (particularly multi-core Xeon processors and Xeon Phi™ coprocessors). The initial target for optimisation and porting work are codes that EPCC are already very familiar with, have had experience parallelising and optimising for standard distributed memory parallel systems, and are used by a wide community of simulation scientists for world leading science in key simulation areas. In particular, we plan to focus on the Energy and Material simulation areas, improving performance and portability of a range of fusion, CFD, and DFT simulation codes.
The centre will build on a range of world-class projects, collaborations, and initiatives that EPCC is currently involved with, including European HPC projects such as PRACE and CRESTA, UK centres of excellence in areas such as Mathematics and HPC (including the NAIS and the Supercomputing Scotland projects), and global simulation initiatives, such as the G8 funded Nu-FuSE project.
A further aim of the IPCC is to leverage the hardware we have available at EPCC, and the extensive training programs we are involved in, to provide training and expertise to a wider range of academic and industrial participants in the UK and Europe on efficiently and effectively using Intel hardware for computational simulation.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804