Sergi Siso is a High Performance Software Engineer in the Hartree Centre, Science and Technology Facilities Council (STFC), Daresbury Laboratory, UK. He is PI of the Hartree Intel® Parallel Computing Center(s) (Intel® PCC). His main role is to analyse the performance, port and optimize scientific and technical applications to novel architectures. Complementary to his job he is coursing a PhD in the Computer Science department of the University of Liverpool, he is researching runtime systems to identify and solve performance issues on the novel many-core architectures.
The key objective of the Intel® PCC at the Hartree Centre is to enable UK academic and industrial codes to exploit the parallel and energy efficient capabilities of Intel systems, and to grow the skill base in both industry and academic institutions.
The key components of this are:
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804