Intel® Parallel Computing Center at Pennsylvania State University

Published: 05/07/2014, Last Updated: 11/27/2017

Principal Investigators:

Prof. Mahmut Taylan Kandemir

Description:

The research at Penn State focuses on application modernization targeting emerging many-core systems. In particular, we investigate custom application mapping and optimization strategies that take into account unique architectural features of Intel® Xeon Phi™ coprocessors. Our research spans code and data optimizations (both application level and compiler level), latency hiding techniques such as prefetching, studying the tradeoffs between native and offload operation modes when running HPC applications, application restructuring techniques that target not only cache misses but also miss latencies, and investigation of novel architectural features that can be critical for future manycore systems (beyond Intel Xeon Phi coprocessors).

Our research will lead to:

  • Identifying required steps for extracting maximum performance from Intel Xeon Phi coprocessors during application mapping and optimization.
  • Understanding whether conventional compiler optimizations (as well as our new optimizations) are effective when targeting large HPC codes, and if not, why.
  • Finding additional problems when mapping applications to a system with multiple Intel Xeon Phi coprocessors.
  • Comparing our results against those that will be collected using available commercial GPU systems.

Publications:

Related websites:

http://www.cse.psu.edu/~kandemir

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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