Prof. Dr. Wolfgang Nagel
An important step towards shorter code development cycles is to help scientists and engineers to increase the parallelism of their applications. The Intel® Parallel Computing Center (Intel® PCC) at the Center for Information Services and High Performance Computing (ZIH) of Technische Universität Dresden carries out two projects that target one important common goal: the automatic generation of optimized parallel code for Intel's many-core architecture with its multiple parallelization levels.
ZIH, T-Systems SfR, and the German Aerospace Center (DLR) will combine forces to bring TAU and TRACE, two leading CFD solvers in the European aerospace industry, to Intel Xeon Phi™ coprocessor and subsequent coprocessors. Both codes will be tuned for optimal performance by leveraging all levels of parallelism provided by Intel Xeon Phi™ coprocessor, thereby making aerospace and CFD research codes ready for next-generation hardware accelerators. In addition, compiler techniques will be examined, to demonstrate a minimally invasive approach to transform a program to a data layout appropriate for the Intel Xeon Phi™ coprocessor.
Along with Bosch-Rexroth and ITI GmbH, ZIH will adapt the Open Modelica Compiler backend to produce code for efficient simulations on Intel Xeon Phi™ coprocessor. The Modelica equation graph may consist of several thousands of equations and may be highly heterogeneous, i.e., the equations are of different complexity. The main challenge is the automatic analysis of that graph and the identification and creation of parallel sections. With the help of cost estimations, both performance optimizations and the scheduling of threads will be prepared at compile time. This approach will allow us to improve simulation speeds on Intel Xeon Phi™ coprocessor, and it will help to meet some of the current demands from industry without the necessity to install large and expensive computer clusters.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804