Intel® Parallel Computing Center at The George Washington University

Published: 03/16/2018, Last Updated: 03/16/2018

Principal Investigators:

Tarek El-Ghazawi- is an ECE Professor at GWU, where he also leads the university strategic excellence program in HPC. His interests include HPC and future processor architectures.    He is one of the principal authors of the UPC parallel language and one of the pioneers of High-Performance Reconfigurable Computing.  He published extensively and his work was sponsored by government and industry. He has served as Associate Editor for IEEE TC and TPDS.  He has chaired many symposia including the IEEE/ACM CCGrid2018, IEEE HPCC, and IEEE PGAS2015.  He is a Fellow of the IEEE and was awarded the Humboldt Research Award.


The GW IPCC center focuses on modern parallel programming for manycore chips and parallel architectures. Areas of specific interest include optimizations, productivity, locality exploitation and Partitioned Global Address Space (PGAS) programming models, applications in high performance computational science and engineering and HPC education.

The group works with domain scientists in many interesting areas including computational neuroscience, and computational science and engineering. Prior work included sponsored research projects in productive locality-aware parallel programming and run-time systems of accelerators including manycore chips and FPGAs and the group will continue some of those efforts under the GW IPCC. In addition, the group will be targeting a number of applications including accelerating brain simulations leveraging its expertise and collaborations in neuroscience and computational neuroscience, PGAS kernels, and VSIPL workloads to name a few.

The GW IPCC will also leverage its DC location and international collaborations for outreach including training and education in the area of productive multicore programming. The outreach will include local/international academia, government, industry and HBCU/MI. The group has designed teaching modules for parallel computing with multi-core chips, in addition to outreaching to the community through offering related short training.


T. El-Ghazawi, W. Carlson, T. Sterling, and K. Yelick, May 2005, UPC: Distributed Shared Memory Programming. John Wiley & Sons Inc., New York

Martial Michel, Olivier Serres, Ahmad Anbar, Edmond J. Golden III, Tarek El-Ghazawi, February 2017, Open Source Private Cloud Platforms for Big Data, In Big Data Analytics for Sensor-Network Collected Intelligence. Academic Press, ISBN: 978-0-12-809393-1.

Achahbar, M Abid, M Bakhouya, C El Amrani, J Gaber, M Essaaidi, T El Ghazawi, 2015, Approaches for Big Data Processing: Applications and Challenges In: Big Data: Algorithms, Analytics, and Applications Edited by:Kuan-Ching Li, Hai Jiang, Laurence T. Yang, Alfredo Cuzzocrea. Taylor & Francis Group, USA: Chapman & Hall/CRC Big Data Series, CRC Press.

Abdel-Hameed Badawy, Gabriel Yessin, Vikram Narayana, David Mayhew, Tarek El-Ghazawi, 2017, Optimizing thin client caches for mobile cloud computing: Design space exploration using genetic algorithms, Concurrency and Computation: Practice and Experience; e4048.

Lubomir Riha, Jacqueline Le Moigne, and Tarek El-Ghazawi, 2016, Optimization of Selected Remote Sensing, IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing vol Algorithms for Many-Core Architectures. 9, no. 12: 5576-5587.

Ahmad Anbar, Olivier Serres, Engin Kayraklioglu, Abdel Hamid Badawy, and Tarek El-Ghazawi, June 2016, Exploiting Hierarchical Locality in Deep Parallel Architectures, ACM Transactions on Architecture and Code Optimizations Volume 13 Issue 2.

Olivier Serres, Abdullah Kayi, Ahmed Anbar and Tarek El-Ghazawi, January 2016, Enabling PGAS Productivity with Hardware Support for Shared Address Mapping: A UPC Case Study, ACM Transactions on Architecture and Code Optimizations, Volume 12 Issue 4.

Abdullah Kayi, Olivier Serres, and Tarek El-Ghazawi, February 2015, Adaptive Cache Coherence Mechanisms with Producer-Consumer Sharing Optimization for Chip Multiprocessors, IEEE Transactions on Computers. VOL. 64, NO. 2, pp 316-328.

Abdullah Kayi, Olivier Serres, and Tarek El-Ghazawi, June 2014, Bandwidth adaptive cache coherence optimizations for chip multiprocessors, International Journal of Parallel Programming, vol. 42, no.3, pages 433–455.

Teng Li, Vikram K Narayana, and Tarek El-Ghazawi, Nov 2013, Exploring Graphics Processing Unit (GPU) Resource Sharing Efficiency for High Performance Computing, Computers, vol. 2, no. 4. pp. 176-214.

Related Websites:

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804