Universities, institutions, and labs that work to optimize open-source applications.
As the world of high-performance computing (HPC) evolves and becomes accessible, use this starting point to optimization and gaining better compute performance. While many applications already use features of modern hardware, many more do not extract parallelism in their algorithms, nor do they leverage other new capabilities including larger caches, Single Instruction Multiple Data (SIMD), threading, fabric technology, new file architecture, and nonvolatile memory technology.
This collection of self-paced training and reference materials provides an overview of parallel programming on Intel® architecture.
Learn how to modernize code for the Intel® Xeon Phi™ processors. Gain insight for OpenMP*, Intel® MPI Library, and Intel® software to write code using better vectorization and parallelism for hardware optimization.
Why Use Code Modernization?
The Purpose of Intel® Many Integrated Core Architecture
Think Parallel: Modern Applications for Modern Hardware
Parallel Programming Models - Tips and Tricks
Deep Dive with Code Modernization Experts
Use these materials to further your knowledge of the Lustre* file system, gain deeper insight into solutions from Intel, and explore fundamental concepts and advanced implementation and configuration details.
The next generation of HPC switch technology, Intel® Omni-Path Fabric (Intel® OP Fabric), is designed for improving system-level packaging and network efficiency. It enables a broad class of computations requiring scalable, tightly coupled processor, memory, and storage resources. These training materials help you become familiar with Intel® OPA.
Next-Generation Fabric: Details on the Intel OPA
Advanced Features of the Intel OPA Network Layers
Democratize Best-in-Class Interconnect Performance
The Intel OPA Launch
Maximize HPC Storage Performance
Access hands-on workshops, code samples, case studies, and domain-focused training to get the most out of your code on Intel architecture. We also encourage you to check out the Intel® Software Innovator and Intel® Black Belt Software Developer Program.
Get continued training for OpenMP*, Intel MPI Library, Intel® Parallel Studio, Intel Xeon Phi processor and coprocessor, expressing parallelism, and performance optimization methods.
Multi-Channel DRAM (MCDRAM) on Intel Xeon Phi Products – Analysis Methods and Tools
How to Detect Intel AVX-512 Support (Intel Xeon Phi Processor)
Scale your Application Across Shared and Distributed Memory
Squashing Races, Deadlocks, and Memory Bugs
Software Defined Visualization: Data Analysis for Current and Future Cyber Infrastructure
Benefits of Leveraging Software Defined Visualization (Intel® OSPRay)
From Correct to Correct and Efficient with Molecular Dynamics Benchmarks
From Correct to Correct and Efficient with Hydro2D
Optimization of Vector Arithmetics in Intel Architecture
Optimization of Multithreading in Intel Architecture
Gain Performance through Vectorization Using Fortran
Exploit Multilevel Parallelism in HPC Applications
Roofline Analysis: Visualize Impact of Compute Versus Memory Optimizations
This advanced training is for anyone who wishes to further their knowledge of the file system and gain deeper insights into solutions from Intel for software. The training exposes you to many implementation concepts and configuration details.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804