Intel® Xeon® Phi™ Processor Performance Monitoring Reference Manual

Published:11/02/2015   Last Updated:03/03/2017

The Intel® Xeon® Phi™ Processor (code name Knights Landing) provides performance monitoring facilities that are a unique combination of Intel® Atom™ processor-like core performance monitoring units (PMU) and Intel® Xeon® processor based server class uncore capabilities.

Performance Monitoring Reference Manual – Volume 1: Registers

Provides an overview of the Intel® Xeon® Phi™ Processor architecture and a description of the tile and untile register and MSR information related to performance monitoring. This document is targeted towards software developers involved in developing device drivers and software agents that wish to perform performance monitoring in the Intel® Xeon® Phi™ Processor.

Performance Monitoring Reference Manual – Volume 2: Events

The Intel® Xeon® Phi™ Processor (formerly code named Knights Landing) provides performance monitoring events. Performance monitoring events in the processor is a unique combination of Intel® Atom™ processor-like core events and Intel® Xeon® processor-based server class uncore events.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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