The Ivy Bridge Performance workshop is a workshop sample illustrating coding best practices for graphics performance on Ivy Bridge architecture. A D3D11 application renders a racing simulation within a stylized city scene. Multiple versions of the sample code are provided which implement progressive performance improvements. A tutorial leads the user through use of Intel Graphic Performance Analyzer tools to identify performance bottlenecks and quantify improvements for each optimization step.
CityRacer came out of the box with some intentional performance problems and their solutions, to be identified and corrected through the course of the workshop.
Since the original sample was released, the Game Technology Development team have created a new cross-platform sample framework, to which we have ported the CityRacer sample. The new framework made it easy to add shadows, a feature desired in the original but that wouldn't quite fit in the performance envelope. Shadows make for both a more visually appealing and a more game-representative workload:
With the new framework and the new features, a completely different set of performance optimizations present themselves. In the original, each optimization was controlled by a individual #ifdef compiler directive, requiring the user to re-compile for each optimization step. For the new version the various optimizations are controlled via checkboxes on the user interface. The user can still examine the source code changes for each of the optimizations, but it's no longer mandatory - flipping the checkbox applies the optimization interactively. The original version focused entirely on frame-rate performance, but this version also recognizes the increasing importance of power management by including a power optimization that can be observed in real time via the Intel GPA System Analyzer tool. The updated CityRacer source zip file is available for download. (Note that this is just a source code update.)
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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804