Code Sample: Allocate Memory Efficiently on an Intel® Xeon Phi™ Processor

By Michael A Pearce,

Published:03/10/2016   Last Updated:03/10/2016

The Intel’s next generation Xeon Phi™ processor family x200 product (code-name Knights Landing) brings in new memory technology, a high bandwidth on package memory called Multi-Channel DRAM (MCDRAM) in addition to the traditional DDR4. MCDRAM is a high bandwidth (~4x more than DDR4), low capacity (up to 16GB) memory, packaged with the Knights Landing Silicon. MCDRAM can be configured as a third level cache (memory side cache) or as a distinct NUMA node (allocatable memory) or somewhere in between. With the different memory modes by which the system can be booted, it becomes very challenging from a software perspective to understand the best mode suitable for an application.

At the same time, it is also very essential to utilize the available memory bandwidth in MCDRAM efficiently without leaving any performance on the table.

The tutorial cover methods and tools for users to analyze the suitable memory mode for an application. These tutorials also cover the use the “memkind” library interface, a user-extensible heap manager built on top of jemalloc. This library interface lets users change their application memory allocations to the high bandwidth MCDRAM as opposed to the standard DDR4.

Video Presentation: MCDRAM on 2nd generation Intel® Xeon Phi™ processor

Tutorial Material (PDF): Downloadapplication/pdf Download

In this tutorial you will be able to:

  • Understand the different modes of MCDRAM and how to use them
  • Identify whether an application can benefit from MCDRAM
  • How to place data structures in MCDRAM
  • How to perform test & emulation of MCDRAM-enabled code on a NUMA machine

The code samples used in the above data structures section are here (ZIP): Downloadapplication/zip Download

Try it yourself!

 

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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