OpenMP* 4.0 Features in Intel C++ Composer XE 2013

Published:01/16/2013   Last Updated:01/16/2013

The current OpenMP* 4.0 RC1 specification and associated TR1 technical report (both available from adds new features for controlling vectorization and execution on coprocessors.

Intel® C++ Composer XE 2013 Update 2 (compiler version 13.1) supports two of these new features regarding the simd and target clauses. These are similar to existing Intel-specific compiler directives.

  1. SIMD pragmas, directives, and clauses
  2. TARGET pragmas, directives and clauses for attached coprocessors (or devices)

Intel® C++ Composer XE 2013 SP1 (compiler version 14.0) adds partial support for OpenMP* 4.0 features including:

  1. TEAMS pragmas, directives and clauses
  2. DISTRIBUTE pragmas, directive and clauses
  3. SIMD pragmas, directives, and clauses
  4. TARGET pragmas, directives and clauses for attached coprocessors (or devices)
  5. #pragma omp taskgroup construct
  6. Atomic clause seq_cst
  7. Six new forms of atomic capture and update:
    1. Atomic swap: {v = x; x = expr;}
    2. Atomic update: x = expr binop x;
    3. Atomic capture 1: v = x = x binop expr;
    4. Atomic capture 2: v =x = expr binop x;
    5. Atomic capture 3: {x = expr binop x; v = x;}
    6. Atomic capture 4: {v = x; x = expr binop x;}
  8. proc_bind(<type>) clause where <type> is “spread”, “close”, or “master”
  9. OMP_PLACES environment variable
  10. OMP_PROC_BIND environment variable
  11. omp_get_proc_bind() API

For detail information pleaser reference to User and Reference Guide for the Intel® C++ Compiler 14.0

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804