Hugues has been passionate about graphics programming since the Commodore* Amiga* demo scene in the mid-1980s. He earned his master in computer graphics from IRISA University and relocated to California to grow two San Francisco bay area start-ups. In 2005, he joined Intel where he worked on optimizations of the geometry pipe for the graphics driver stack, followed by shader compiler architecture and end-to-end optimizations of the Larrabee graphics pipeline. More recently, he worked on an end-to-end VR compositor, including design, architecture, implementation, and optimizations for the Project Alloy VR headset.
Working on competitive graphics innovation for future Intel platforms, his current research focus is advancing state-of-the-art real-time rendering, ray-tracing GPU acceleration, and GPU compiler and hardware architecture.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804