Scheduling for 1-4 Threads Per Core Using Compiler Option -qopt-threads-per-core

Published: 10/16/2013, Last Updated: 10/16/2013

Compiler Methodology for Intel® MIC Architecture

Scheduling for 1-4 Threads Per Core Using Compiler Option -qopt-threads-per-core

This option is a hint or suggestion to the compiler about the number of hardware threads per core that MAY be used for an application. This hint enables the compiler to perform better code optimizations (such as instruction scheduling).

-qopt-threads-per-core=1/2/3/4 (default is 4)
  • This option does not affect the number of threads/core that will be used at run time.  That will be controlled by settings such as KMP_AFFINITY, OMP_NUM_THREADS, KMP_PLACE_THREADS, etc.
  • Code compiled with this option can run correctly on any (hardware supported) number of threads/core

Gives a hint to the compiler about how many threads are likely to be running on the core for the application. This information is used to optimize more effectively, especially during instruction scheduling. The value of N should be chosen by the user to match how many threads will be used per core while executing the application. For example, if the application is parallelized using OpenMP, use the value of N for the number of threads-per-core as the OpenMP affinity setting to be used when executing the application code on Intel MIC Architecture. Please refer to the Intel


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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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