In this chapter, we examine the Intel Compiler Heterogeneous Offload programming model for the Intel® MIC Architecture.
The Intel® C/C++ Compiler and Intel® Fortran Compiler support a programming model known as "Heterogeneous Offload". In this model, the programmer designates code sections to run on the Intel® Many Integrated Core Architecture (Intel® MIC Architecture) target device. The Hetergeneous Offload model uses simple pragmas/directives and optional C++ language extensions to specify code sections and data to offload to the Intel® MIC Architecture target device(s). No further special programming API is needed, just simple pragmas and optional C++ language extensions. All setup/teardown, data transfer, and synchronization is managed by the compiler and runtime. In this model, the application starts on the host platform. When a offload region is encountered, two actions can occur. If a supported Intel® MIC Architecture target is found and is available, the offload region and data is transferred (if needed) and run on the target device. If for some reason there is no available MIC target, the code region is run on the CPU.
In the heterogeneous model, the host application and MIC target device do not share memory. Two techniques are used to deal with the independent memory spaces:
The Heterogeneous Offload Model for Intel® Many Integrated Core Architecture is a presentation with a good overview of the Heterogeneous Offload model.
Tutorials: the "Getting Started" document that is included in the documentation for your compiler has a tutorial with code samples in Fortran and C++ demonstrating heterogeneous offload. Open this "Getting Started" document, look for the reference and links under the topic "Tutorials" for the tutorial named "Using the Intel® MIC Architecture". Follow along with the samples provided with your compiler. If you don't know where to find your compiler's documentation and samples, revisit the chapter New User Compiler Basic Usage.
Samples: Like the tutorials, extensive samples for heterogeneous offload are provided with your compiler. Visit New User Compiler Basic Usage if you do not know where to find your Samples directory.
Offload Usage and Syntax: Product documentation on use of heterogeneous offload model and syntax reference is included in your "Intel® Compiler XE User and Reference Guides" which is installed on your system with the compiler and is available online (after September, 2012). From the Contents navigation toolbar of your User and Reference Guide, open "Key Features", "Intel® MIC Architecture", "Programming for Intel® MIC Architecture", "Overview: Heterogeneous Programming" and follow the documentation links. If you don't know where to find your compiler's documentation and samples, revisit the chapter New User Compiler Basic Usage.
Late Breaking Additions or Changes: visit your Release Notes document for your compiler. This document is available along with the product download from your account at https://registrationcenter.intel.com. It is also packaged and installed with your compiler (see New User Compiler Basic Usage )
Also, visit your Intel MIC Architecture Developer community portal at http://software.intel.com/mic-developer for up to the minute information.
Need more help? If you have further questions or the above documentation does not cover your application's usage model, or you want assistance with your application, please visit the Intel(R) Many Integrated Core Architecture User Forum.
The Intel Compilers support a programming model known as "Heterogeneous Offload". In this model, the programmer designates code sections to run on the Intel® Many Integrated Core Architecture (Intel® MIC Architecture) target device. The Hetergeneous Offload model uses simple pragmas/directives and optional C++ language extensions to specify code sections and data to offload to the Intel® MIC Architecture target device(s).
There are many avenues to explore this model. The compiler product includes:
It is essential that you read this guide from start to finish using the built-in hyperlinks to guide you along a path to a successful port and tuning of your application(s) on the Intel® Xeon Phi™ coprocessor. The paths provided in this guide reflect the steps necessary to get best possible application performance.
Back to the chapter "Native and Offload Programming Models"
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
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