Training Sample: Intel® Advisor Roofline

By Alexandra Marie Shinsel,

Published:11/26/2018   Last Updated:11/26/2018

Note: This sample is intentionally broken for training purposes.

Note: Due to the extremely hardware-dependent nature of the Intel® Advisor Roofline feature, we make no guarantees that the code provided will behave as predicted on your machine. This code is not being updated, as it is intended to match the provided pre-collected results, which have been generated on a machine known to behave as shown in the media using this sample. Please use the provided results when following the tutorials to guarantee the intended behavior.

File(s):

Download Source Code
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License: Intel Sample Source Code License Agreement
Optimized for...  
OS: N/A (Results collected on Microsoft* Windows* 10)
Hardware: N/A (Results collected on Intel® Core™ i5-6300U CPU)
Software:
(Programming Language, tool, IDE, Framework)
C++, Intel® Advisor
Prerequisites: Requires Intel® Advisor 2017 Update 2 or later. Source code intended for use with Intel® C++ Compiler version 17.0 and requires an Intel® processor with AVX2 instruction set support.

Introduction

This sample, used in the Intel® Advisor Roofline walkthrough video and tutorial, is intended to demonstrate how to use the Intel® Advisor automated Roofline chart to visualize actual performance against hardware-imposed performance ceilings, as well as determine the main limiting factor (memory bandwidth or compute capacity), thereby providing an ideal roadmap of potential optimization steps. Each loop has multiple versions, each with successive optimizations made, so that optimized and unoptimized loops exist side-by-side, allowing them to appear together on the Roofline chart without the use of result comparisons.

Resources

Intel® Advisor Roofline Tutorial

Intel® Advisor Roofline Walkthrough Video

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804