Vectorization Advisor is one of the two major features of the Intel® Advisor XE 2016 product. Intel® Advisor XE comprises Vectorization Advisor and Threading Advisor.
Vectorization Advisor is an analysis tool that lets you identify if loops utilize modern SIMD instructions or not, what prevents vectorization, what is performance efficiency and how to increase it. Vectorization Advisor shows compiler optimization reports in user-friendly way, and extends them with multiple other metrics, like loop trip counts, CPU time, memory access patterns and recommendations for optimization.
Intel® Advisor XE version 2015 and earlier had only Threading Advisor workflow. Read more on the product website.
Starting from Intel® Advisor XE 2016, the product includes two major workflows or feature sets:
Vectorization Advisor supports C/C++ and Fortran programming languages.
Vectorization Advisor requires Intel Compiler 15.0 or later to collect full set of analysis data. However, a subset of metrics is available for binaries built with GCC* or Microsoft* compiler.
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Start from running Survey analysis – it will give you main statistics about vectorized and scalar loops:
First things to look at the Survey Report:
“advixe-cl --help” command to learn about syntax and see some examples. Please be aware that Intel Advisor XE 2016 documentation for command line syntax may not be up to date, and not all CLI options may be covered. We’re working on addressing this gap.
Hint: use “Command Line” link on workflow to generate command line for selected analysis type and project settings:
Yes, Vectorization Advisor has multiple features to detect inefficient usage of SIMD instructions. Some typical examples:
Yes. Use command line syntax for analyzing MPI applications, see details and examples. Below is an example with
“-gtool” option. This command launches
“./your_app” application on 4 ranks, and only ranks 2 and 3 are analyzed by Intel Advisor:
mpirun -n 4 -gtool "advixe-cl -collect survey:2,3" ./your_app
You can perform an MPI analysis only through the Intel Advisor command line interface; however, there are several ways to view an Intel Advisor result:
advixe-cl -report survey –project-dir ./my_proj
Vectorization Advisor requires Intel Compiler to collect full set of analysis data. However, a subset of metrics is available for binaries built with GCC or Microsoft compiler:
No. Vectorization Advisor does not require source code modification. You can select loops for analysis using checkboxes on Survey tab:
Source code annotations are needed for Threading Advisor only.
In GUI, you can select loops for analysis using checkboxes on Survey tab:
In command line, print survey report and notice column “ID” before each loop:
advixe-cl -report survey –project-dir ./my_proj
ID Function Call Sites and Loops Self Time Total Time
69 -[loop at test.cpp:190 ...] 1.06054 1.06054
83 -[loop at test.cpp:89 ...] 0.841134 0.841134
51 -[loop at test.cpp:113 ...] 0.799016 0.799016
Then use “-mark-up-list” option to specify loop IDs for Dependencies or Memory Access Patterns analysis:
advixe-cl -collect map -mark-up-list=83,51 -project-dir ./my_proj -– my_application
Tip: open the result in GUI, select loops using checkboxes and press “Get Command Line” button. It will generate command line for Dependencies or Memory Access Patterns analysis automatically.
Survey analysis in Vectorization Advisor is the least intrusive and should not slow down application significantly. However, analyses like “Dependencies” and “Memory Access Patterns” have significant overhead. You can mitigate application slowdown in several ways:
Key Vectorization Advisor features include a:
Tip: Workflow panel helps to navigate through the steps and analysis types.
Most statistics is gathered by Survey analysis. It combines dynamic analysis (CPU sampling), static binary analysis (instruction set, data types, etc.) and compiler diagnostics. All analysis types include binary instrumentation and dynamic analysis; it means that Intel Advisor has to execute an application, even if collecting some data doesn’t require actual running.
The Survey Report provides a wealth of information, including the following:
Trip Counts analysis counts minimum, maximum, median trip counts (i.e. number of times loop body was executed) and call counts (number of times loop is invoked) for all the loops in the application. Therefore, you should to run Survey first, then Trip Counts analysis. NOTE! Do not re-build your binary between running Survey and Trip counts, it can produce wrong results. Trip Counts results are added to existing Survey report in a new column group:
Dependencies analysis checks for cross-iteration (“loop carried”) dependencies. The most common case to use it is when you see “assumed dependence prevents vectorization” message in “Why No Vectorization” column. If Dependencies analysis reports no dependencies, you are safe to force vectorization. If dependencies are detected, you will get detailed information where they are:
NOTE! Dependencies analysis is only applicable to scalar (not vectorized) loops.
Memory Access Patterns (MAP) analysis traces memory access instructions and detects patterns: unit stride, non-unit “constant” stride (like on the picture below) and non-unit variable stride (gather-scatter patterns). Operand size and non-aligned data accesses are also reported.
Example results of MAP analysis in source view:
Run Memory Access Patterns (MAP) analysis in the following cases:
By default, Intel Advisor stores only the most recent result. That means if you run Survey (or any another analysis) two times, you will see only the last one without an option to get back to initial experiment.
You can manually save Intel Advisor experiments using “Snapshot” button in Result window or on product toolbar:
This will save all analyses results (Survey, Trip Counts, Dependencies and MAP) in read-only experiment folder. You will be able to browse it any time, further experiments will not overwrite it. You can access the historical snapshots using Project Navigator.
Intel Advisor has complex structure of result versions. There are four analysis types: Survey, Trip Counts, Dependencies and Memory Access Patterns. All the results are comprised in “experiment” folder, usually called “e000”. The experiment contains the most recent versions of each result type. By default, only one (latest) experiment version is stored, however you can create “snapshots” – historical copies of the current experiment for future analysis and comparison purposes.
Basic analysis type is Survey. All other analysis types depend on Survey results, but don’t depend on each other:
Survey <- Trip Counts
Survey <- Dependencies
Survey <- MAP
Different analysis types are matched by an address in the target application binary. That means, when you select loops in Survey for further Dependencies analysis, they are identified by the address in binary. Changing the binary (re-building) between running Survey and Dependencies will break this connection and results will be wrong. Same applies to MAP and Trip Counts analyses. So if a binary is changed, run Survey again before running other analysis types.
You may run Survey 5 times, and only 1 time run Dependencies (say for Survey result #2). In this case, recent Survey will not match the Dependencies report, they can apply to different binary versions. If it is important to keep them matched, make a Snapshot before updating binary and running further analyses.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
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