Intel® XED is a software library (and associated headers) for encoding and decoding X86 (IA32 and Intel64) instructions. It is widely used inside and outside of Intel. The decoder takes sequences of 1-15 bytes along with machine mode information and produces a data structure describing the opcode and operands, and flags. The encoder takes a similar data structure and produces a sequence of 1 to 15 bytes. Disassembly is essentially printing pass on the data structure produced by the decoder.
The Intel XED examples also include binary image readers for Windows PECOFF, ELF, and Mac OSX MACHO binary file formats (32b and 64b). These allow Intel XED to be used as a simple disassembler. The Intel XED disassembler supports 3 output formats: Intel (dest on left), ATT SYSV (dest on right), and a more detailed internal format describing all resources read and written.
Intel XED compiles with all major compilers and O/Ses and was designed for portability. If required, Intel XED can be built without the encoder or without the decoder to reduce the code/data footprint. The code in the Intel XED library is written in C and is partially generated from tables using python scripts at build time. Intel XED is designed for embedding and has a minimal set of simple external dependencies. It makes no system calls and allocates no memory. It is multithread-safe after one-time initialization of the tables.
Both the 32b and 64b versions of the library can decode or encode 32b and 64b instructions. The machine mode for decoding the instructions is specified in a data structure that is input to the encoding and decoding APIs.
History with Distribution by the Intel Pin project
Until mid-2015, Intel XED had been distributed externally via Pin kits. However, with a recent change to Pin's C-runtime, it is now required that users of Intel XED obtain Intel XED github. The Intel XED library that comes with Pin is compiled to work only with the Pin C-runtime and not the standard runtime libraries available on every system.
Questions and comments can be sent to the Intel ISA Extensions forum.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804