Advanced Computer Concepts For The (Not So) Common Chef: Introduction

Published: 02/20/2015, Last Updated: 02/20/2015

While talking to a very intelligent but non-engineer colleague, I found myself needing to explain the threading and other components of the current and next generation Intel® Xeon Phi™ architectures. The first topic that came up was hyper-threading, and more specifically, the coprocessor’s version of hyper-threading. Wracking my brain, I finally hit upon an analogy that seemed to suit: the common kitchen.

Image of cook, oven & appliances




After grasping hyper-threading in the processor, she asked follow-on questions, extending our discussion. As the conversation continued to evolve, I realized that the kitchen was turning out to be an excellent way of explaining, in an intuitive and (relatively) non-technical way, how the processor worked in a general sense, and what the new innovative features the Knights family of processors brought to the table. The Knights family includes the former Knights Corner, now known as the Intel® Xeon Phi™ coprocessor, the next generation Knights Landing product family, and the generation beyond that, Knights Hill.

This series of blogs should be a lot of fun for me, and hopefully for you as well. We’ll discuss processor pipeline, memory hierarchy, types of memory, hyper-threading, and lots more. At some point, I may even dare to look at some other more abstract concepts, such as Amdahl’s Law.

In and of itself, this isn’t a unique analogy. If you plumb the vast depths of the web, different forms of the kitchen analogy appear relatively frequently. So what am I bringing to the table? Well, I’m going further and will not just explain the basics of how a computer works but details of the underlying technology. I’m also going to use, as a case example, the workings of the Intel® Xeon Phi™ product families. By product family, I’m referring not just to the current generation Intel® Xeon Phi™ coprocessor (a.k.a. Knights Corner) but also the next generation processor and coprocessor families (a.k.a. Knights Landing). Though I won’t be able to discuss KNL specifics that aren't public, there’s a lot of good information out there that is public.

I know what many of you are thinking. “Hey, I’m not a novice but a technical sophisticate. Is this series going to have anything for me?” Personally, I think so. Reading and taking tests about TLBs, interconnects, and the like in an architecture class is one thing; developing an intuitive understanding is quite another. I certainly know that I’ve been learning things by writing this series. If you get excessively bored, I give you permission to not read the rest of my kitchen blogs. I promise not to be offended.

Here’s what the series is looking like at this point. Things will change as the series progresses, as they always do.

  1. An aside on threads and the CPU
  2. Kitchen computing: mapping a kitchen and the chef to a computer system
  3. Hyper-threading and multiple chefs in the kitchen
  4. Memory hierarchy and the well-stocked pantry
  5. Adaptive threading and the adaptive kitchen
  6. The high-bandwidth pantry
  7. Prefetching and caching in the kitchen
  8. The restaurant kitchen and interleaving
  9. So many pantries and the TLB

My hope is that this series will be just as useful to the techie, as to the casual reader who wishes to know more about what makes a computer tick. It will briefly cover topics that are broad and general, e.g., what the CPU and memory are, before diving deeper in to more advanced (and interesting) topics that even the casual programmer may not be that familiar with, e.g., TLBs. Ultimately, the series will drop into topics that introduce the advanced and unique features of the next generation Intel® Xeon Phi™ product.

The first blog in the series (outside of this introduction) will be about clarifying what a thread and CPU actually are. After that, we will start building our kitchen.


Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804