Previously refered to as "Bull Mountain", the RdRand instruction will present itself on the upcoming "Ivy Bridge" platform coming out early 2012. The RdRand instruction paves the way to fast, reliable entropy generated on the processor resulting in highly robust random numbers!
What is a Random Number Generator (RNG)? It is a utility or device that produces a sequence of numbers on an interval such that values appear unpredictable (hopefully!) Each value must be statistically independent of the previous value, the overall distribution of number chosen from the interval are uniformly distributed and the sequence is unpredictable. Additionally, we would like the RNG to be fast in returning a value and it should be highly scalable (it should produce a large number of requests within a short time interval.) It should also be secure against attackers who might observe or change its underlying state in order to predict or influence its output or interfere with its operation.
With respect to the taxonomy of Random Number Generators, here are a few of the different types:
Finally, what IS Bull Mountain, the technology??
Mostly, Bull Mountain follows the Cascade Construction RNG model, using a processor resident entropy source to repeatedly seed a hardware-implemented CSPRNG. Unlike software approaches, it includes a high-quality entropy source implementation which can be sampled quickly to repeatedly seed the CSPRNG with high quality entropy. It represents a self-contained hardware module that is isolated from software attacks on its internal state resulting in a solution that achieves Random Number Generation objectives with considerable robustness: Statistical quality, highly unpredictable random number sequences, high performance, protection against attacks.
The Digital Random Number Generator (DRNG) is unique in its approach in that it is implemented in hardware on the processor chip itself and is available to software running at all privilege levels (even to VMs!!)
Bull Mountain also leverages a variety of cryptographic standards to ensure the robustness of its implementation and to provide transparency in its manner of operation. These include NIST SP800-90, FIPS-140-2, and ANSI X9.82.
About the RdRand instruction:
The Bull Mountain Software Implementation Guide was recently made available on the Manageability and Security Community. Oddly enough, however, this is not the first time we have revealed what it is and how to implement it. It has been documented in the Intel® AVX web page under section 8.6 for quite a long time and it is also referenced in the Intel® 64 and IA-32 Architectures Software Developer’s Manual. Don't have hardware yet to test your implementation? Don't worry, there is a Software Developer Emulator that supports the RdRand instruction out there on our "Whatif" website. Note, that through emulation, you will NOT be able to test actual results and performance - that must be done on actual hardware.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804