Out of the Box Network Developers Newsletter – August 2017

By Sujata Tibrewala, Published: 08/23/2017, Last Updated: 08/23/2017

July was a busy month at the Intel® Developer Zone. Training was held in Santa Clara and Italy, three new network innovators were on-boarded and we’ve been busy planning meet ups and dev labs for the remainder of the year. If you missed out on what we and our developers have been doing, here is a rundown of all the happenings.

OpenStack* Seventh Birthday Celebration

On July 27, Intel hosted the OpenStack* seventh birthday party. The meetup was held in the auditorium of the Intel Altera campus. Presenters from the Linux Foundation* and Intel were featured, and speakers and attendees had the opportunity to attend two of three hands-on labs about the Internet of Things (IoT), Containers or Network Services Benchmark (Intel Hands-on Lab), ETSI/OPNFV Plug-fest (Intel partners). The closing session of the day was the keynote given by Uri Elzur, CTO, Intel. Uri talked about the “Meaningful and Necessary Operation on behalf of NFV and MANO”. The evening birthday celebration kicked off with lightning talks from the sponsors of the day: Intel, Kumulus Technologies*, Cisco DevNet*, Datera*, Mirantis*, Rackspace*, Trilio*, VMware* and the OpenStack Meet-up* groups from the San Francisco Bay Area and San Diego. Sujata Tibrewala used the lightning talk to discuss platform optimizations for Intel® Xeon® processor with vector packet processing (VPP)* (soft switch from CISCO). The evening ended with everyone enjoying delicious cupcakesVideos of the OpenStack seventh birthday event can be found on the SF Bay Area OpenStack User Group YouTube Channel.

Welcome New Intel® Software Innovators

Three new Intel® Software Innovators on-boarded from attendees of Fast Packet Processing in VNF Using DPDK and fd.io Tutorial at IEEE SDN Net soft (July, Italy)

  • Shohreh Ahvar, PhD student, Institut Mines Telecom, Telecom SudParis in co-accreditation with the Pierre and Marie Curie University (Paris 6) on the topic of cloud-based content delivery networks working on Ericson-funded projects. Her research interests are network function virtualization, content delivery networks, cloud computing and wireless sensor networks.
  • Mohammad Shojafar, Senior researcher at the University of Rome Tor Vergata to work on the 5G Superfluidity project (Consorzio Nazionale Interuniversitario per le Telecomunicazioni), Rome, Italy.
  • Marco Spaziani Brunella, Research associate for CNIT/University of Rome Tor Vergata. Background in RTL system design and is currently focused on CPU architectures for network packet/flow processing.

Upcoming Events:

22 August 2017 – Dublin, Ireland

Platform Transformation for NFV and SDN

Come learn about some of the technologies that are instrumental in the platform transformation for NFV and SDN. 

28 August 2017 – Portland, OR

Reality of SDN, OpenStack EPA and Containers

Stephen Hemminger, principal software engineer at Microsoft and a Linux* developer is the featured speaker at the next Portland meet up. As maintainer of the Linux bridging and the iproute2* utilities, Stephen contributes regularly to the Linux kernel and DPDK projects.

19-20 September 2017 – San Jose, CA

Intel® Developer Zone SDN/NFV Network Developer Lab

Call for demos and talks is open.  Email your proposal before September 1, 2017.

Hands-on Labs planned

  • OpenStack EPA (Enhanced Platform Awareness with Network Services Benchmark example VNFs)
  • OpenStack OpenDaylight*
  • New model for cloud network function development: YANFF (yet another network function framework)
  • Demo: Kuryr + OpenDaylight that provides the ability to deliver networking for virtual machines (VM) and containers that enable microservices

The lab is free to attend but you must apply for consideration.

6-8 November 2017 – Berlin, Germany

The Third International Workshop on Security in NFV-SDN

Tutorial: Clear Containers VNF (Speakers: Manohar Castilino, Eric Ernst (both from Intel) and Shohreh Ahvar, Intel Innovator).

6-8 November 2017 – Berlin, Germany

IEEE Conference on Network Function Virtualization and Software Defined Networks

Tutorial: Fast Packet Processing Towards Scalable and Agile VNFs. Speakers: Sujata Tibrewala, Muthurajan Jayakumar, Manohar Castelino , and Sundar Vedantham.

This tutorial is part of Berlin 5G week

At our meet ups, you will interact with and learn from experts at the forefront of the SDN and NFV revolution. Register for our hands-on labs and tech talks, and participate in our on-site network developer challenges for cool prizes. For more information, go to Out of the Box Network Developers.

New on Intel® Developer Zone

Check out the following new content and more at the Intel Developer Zone Networking site.

Video tutorial series playlist Intel® Clear Containers Overview is now on the ISTV YouTube* channel, featuring Amy Leeland and Manohar Castelino. Includes three videos:

  • Intel Clear Containers Overview, featuring Amy Leeland
  • Intel Clear Containers: How We Made Them Smaller and Faster Part 1, featuring Manohar Castelino
  • Intel Clear Containers: How We Made Them Smaller and Faster Part 2, featuring Manohar Castelino

The Open vSwitch* Exact-Match Cache

The Exact-Match Cache is the first and fastest mechanism used by Open vSwitch* (OVS) to determine what to do with an incoming packet. See its role in the OVS workflow and learn about its key features.

Get Started with IPsec* Acceleration in the FD.io VPP Project.

Learn how FD.io, VPP, and the DPDK Cryptodev library work together to provide enhanced IPsec* performance and functionality. Configuration instructions are included.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804