Parallel Universe Magazine Issue 38: See You at the Intel® HPC Developer Conference

By Henry A. Gabb, Published: 10/09/2019, Last Updated: 10/09/2019

Before we get started, I have a couple of news items to pass along. First, the Intel® HPC Developer Conference returns to Denver, Colorado, November 17 and 18, just before SC19. Second, there's a new book you'll want to check out: Pro TBB: C++ Parallel Programming with Threading Building Blocks. It was written by Intel's Michael Voss, Rafael Asenjo from the University of Malaga, and the editor emeritus of The Parallel Universe, James Reinders. If you’ll be in Denver next month, stop by the developer conference or the Intel booth at SC19. I’d like to hear your thoughts on the magazine and topics you want us to cover next year. You can also meet the authors of the book and learn more about TBB.

In this issue, our feature article, Accelerated XGBoost* for Intel® Xeon® Processors, describes a series of optimizations that dramatically improve the performance of the popular XGBoost machine learning library. 

Next, we have Detecting and Mitigating False Sharing in Multi-Processors. False sharing is a subtle performance bug that limits parallel scalability. This article shows you how to detect and fix this problem using Intel® VTune™ Amplifier.

If you straddle the worlds of HPC and data analytics, you'll want to read Speeding Up Simulation Analysis with yt* and Intel® Distribution for Python*, written with our collaborators at the Leibniz Supercomputing Centre. This article shows how they improved post-processing performance using the Intel® Distribution for Python and yt, “a community-developed analysis and visualization toolkit for volumetric data.”

If you’re interested in improving the security of your software, we have an article on Intel® Software Guard Extensions that describes the secure enclave model and provides simple code examples illustrating how enclaves are created and used.

We close out this issue with two editorials: one from Dennis O’Connell, Senior Director of Performance Engineering at Verizon and another from me. 

The first one discusses how Verizon maximizes customer satisfaction using programming tools like Intel® Parallel Studio XE and Intel® System Studio

You may remember this article from over two years ago: Julia: A High-Level Language for Supercomputing (The Parallel Universe, Issue 29). We close this issue with an editorial I wrote about Composable Threading Coming to Julia*. Composability allows a program to spawn threads freely without worrying about oversubscribing the hardware because the runtime scheduler sorts everything out. It’s a powerful new feature of the language. It’s hard to predict whether Julia will succeed in the saturated marketplace of programming languages, but with over 10 million downloads and 3,000 packages, it appears to be gaining popularity. I’ll try to get an updated article from the Julia developers for a future issue of The Parallel Universe.

As always, don’t forget to check out Tech.Decoded for more information on Intel's solutions for code modernization, visual computing, data center and cloud computing, data science, and systems and IoT development.

Hard to believe, but this is our last issue of 2019. We're looking forward to bringing you lots more in 2020.

Henry A. Gabb
October 2019


Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804